Monolithic Power Systems Inc. MP6922DSE-LF-P

Overview

MP6922DSE-LF-P from Monolithic Power Systems is a dual-channel fast turn-off intelligent synchronous rectification controller for LLC resonant converters, driving two N-channel MOSFETs with 70mV V_DS regulation, 20ns total turn-off delay, and integrated reverse current protection. It supports CCM, CrCM, and DCM operation modes and delivers <600µA quiescent current in light-load latch-off mode for AC-DC adapters and telecom SMPS.

For engineers reviewing the MP6922DSE-LF-P datasheet, MP6922DSE-LF-P pinout, MP6922DSE-LF-P application, or MP6922DSE-LF-P equivalent, key selection criteria include V_DS regulation accuracy (55–85mV), RCP threshold (3V), SOIC8 package thermal resistance (θ_JA = 90°C/W), and EN/LL pin timing control for burst-mode efficiency optimization.

Technical Context

The MP6922DSE-LF-P implements dual independent channel control with adaptive gate drive blanking: 1µs turn-on blanking (adjusting off-threshold to +100mV) and 1.6µs turn-off blanking to suppress false triggering. Each channel senses drain-to-source voltage via dedicated VD/VS pins and regulates conduction to maintain ~70mV forward drop.

Its reverse current protection (RCP) function monitors voltage at the RCP pin using an internal 5V reference; when threshold exceeds 3V, both gate drivers are latched for 100µs. The LL pin enables external resistor-based light-load timing adjustment (T_LL = 2.2µs × R_LL/100kΩ), supporting burst-mode operation in low-power standby.

Key Specifications

Pinout & Package

MP6922DSE-LF-P is housed in an 8-pin SOIC package (SOIC8) with exposed pad not present-distinct from SOIC8E. Pin 1 is VG2 (Channel 2 gate driver output); Pin 8 is VG1 (Channel 1 gate driver output). PGND (Pin 1) and VSS (common source reference) are internally connected but require separate PCB routing for noise isolation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel synchronous rectification controller applications.

Compared with MP6923DSE-LF-P, MP6922DSE-LF-P provides true dual-channel independence essential for center-tapped LLC, while versus UCC24612DR it delivers superior timing precision (20ns vs. 40ns), tighter regulation (70mV vs. 100mV), and integrated RCP-reducing BOM and improving robustness in high-reliability telecom and industrial applications.

Availability

MP6922DSE-LF-P is available at Aetrix Electronics and suitable for AC-DC adapters, LCD/PDP TV power supplies, and telecom SMPS requiring stable component supply, RoHS-compliant packaging, and long-term lifecycle support.

Supply support for MP6922DSE-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP6922 belongs to MPS's Intelligent Synchronous Rectifier Controller product line, engineered specifically for high-efficiency LLC resonant converters in energy-sensitive consumer and telecom power applications.

FAQ

What is the maximum recommended PCB copper area for the exposed pad on MP6922DSE-LF-P?

MP6922DSE-LF-P uses a standard SOIC8 package without an exposed thermal pad-unlike the SOIC8E variant. Therefore, no thermal pad copper area is applicable. Thermal management relies on θ_JA = 90°C/W via standard SOIC8 land pattern and 2oz copper layers per the datasheet layout guidelines.

Can MP6922DSE-LF-P drive logic-level MOSFETs directly without gate resistors?

Yes-MP6922DSE-LF-P's gate drivers support both standard and logic-level N-MOSFETs. Its 3A pull-down strength and 0.05–0.1V low-state voltage ensure reliable turn-off of logic-level devices (V_GS(th) ≤ 2.5V), though small series gate resistors (≤10Ω) are still recommended to dampen ringing in high-dI/dt layouts.

How does the LL pin affect light-load behavior in MP6922DSE-LF-P?

The LL pin sets light-load timing via an external resistor: T_LL = 2.2µs × R_LL/100kΩ. This determines the pulse width threshold for entering latch-off mode. A 100kΩ resistor yields the default 2.2µs, while higher values delay light-load entry, optimizing efficiency for specific load-step profiles in burst-mode operation.

Is reverse current protection (RCP) active in all operating modes?

Yes-RCP is always enabled and functions identically in CCM, CrCM, and DCM. When the RCP pin voltage exceeds 3V (indicating reverse current), both gate drivers are latched for 100µs regardless of mode. This ensures consistent protection during transient overload or abnormal startup conditions.

What is the minimum V_DD required to sustain gate drive output?

V_DD must remain above 5.0V (UVLO rising threshold) to maintain gate drive functionality. Below this, the IC enters sleep mode and pulls VG1/VG2 low via internal 10kΩ resistors. Stable operation requires maintaining V_DD ≥ 8V per recommended conditions, with sufficient bulk capacitance to ride through line dips.

Does MP6922DSE-LF-P support interleaved LLC topologies?

No-MP6922DSE-LF-P is designed for single-phase LLC resonant converters with center-tapped or full-wave rectified secondaries. It lacks phase synchronization inputs or multi-phase timing coordination features required for interleaved operation, which would necessitate discrete timing alignment or a different controller family.

How is thermal shutdown recovery handled in MP6922DSE-LF-P?

Thermal shutdown triggers at 150°C junction temperature, pulling VG1/VG2 low. Recovery occurs automatically when junction temperature falls to 120°C (30°C hysteresis), restoring normal gate drive without requiring EN pin cycling or external reset-ensuring graceful recovery during temporary thermal overload.