Monolithic Power Systems Inc. MP6925GS-P

Overview

MP6925GS-P from Monolithic Power Systems is a dual-channel, fast-turn-off synchronous rectifier IC for LLC resonant converters, driving two N-channel MOSFETs with 35ns total turn-off delay, regulating forward voltage drop to 29mV (typ), and supporting CCM/CrCM/DCM operation across 4.2V–35V VDD. It enables high-efficiency secondary-side rectification in isolated AC/DC power supplies.

For engineers reviewing the MP6925GS-P datasheet, MP6925GS-P pinout, MP6925GS-P application, or MP6925GS-P equivalent, key selection criteria include light-load latch-off timing (programmable via LL pin), noise-immune VD sensing up to 180V, dual-channel independent gate drive (VG1/VG2), and SOIC-8 thermal performance (θJA = 90°C/W).

Technical Context

The MP6925GS-P implements adaptive zero-current detection using differential VD1/VSS and VD2/VSS sensing to regulate MOSFET conduction at −29mV forward drop, with blanking windows (tB_ON = 1.1µs, tB_OFF = 1750ns) preventing false triggering during switching transients. Its control logic independently manages each channel's turn-on and turn-off based on real-time drain-source voltage polarity and magnitude.

It integrates a programmable light-load mode triggered by VG1 pulse-width monitoring against VLL-GS = 0.6V threshold, with enter delay (tLL-D = 78µs typ) and hysteresis (tLL-H = 0.45µs), latching both gate drivers off to reduce quiescent current to 175µA. UVLO (3.95V rising) and thermal shutdown (175°C, 10°C hysteresis) provide system-level protection.

Key Specifications

Pinout & Package

MP6925GS-P is housed in an SOIC-8 package with exposed PGND pad for thermal and electrical performance. Pin 2 (PGND) serves as the primary power ground return, while Pin 5 (VSS) is the signal reference for both VD1 and VD2 sense inputs - critical for accurate differential forward-voltage detection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel LLC synchronous rectifier applications.

Compared with NCP4306DR2G and UCC24612-2, MP6925GS-P delivers integrated dual-channel control, faster turn-off, and programmable light-load optimization - reducing component count and improving light-load efficiency in compact multi-output LLC converters.

Availability

MP6925GS-P is available at Aetrix Electronics and suitable for AC/DC adapters, PC power supplies, and LCD/LED TV power stages requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.

Supply support for MP6925GS-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design centers in the US, China, and Taiwan.

The MP6925 product line targets high-efficiency LLC resonant converter secondary-side control, emphasizing fast transient response, noise immunity, and multi-mode compatibility for next-generation power supplies.

FAQ

What is the maximum V_D voltage the MP6925GS-P can safely sense?

The MP6925GS-P supports V_D voltages from −1V to +180V relative to VSS, as specified in Absolute Maximum Ratings. This allows direct connection to high-voltage secondary windings in 48V–54V output systems without external voltage dividers or clamping circuits.

How does the light-load latch-off function improve efficiency?

The light-load function monitors VG1 pulse width against VLL-GS = 0.6V; if pulses remain below threshold for longer than tLL-D (78µs typ), both gate drivers latch off, reducing quiescent current to 175µA. This cuts standby power in Energy Star-compliant adapters and PC PSUs.

Can MP6925GS-P drive both high-side and low-side synchronous rectifiers?

Yes - its dual independent channels (VG1/VG2 with VD1/VSS and VD2/VSS) support either configuration. High-side use requires floating gate drive referenced to MOSFET source (VSS), while low-side uses grounded source; both are validated in MPS application notes.

What is the recommended PCB layout practice for VD sensing?

VD1/VSS and VD2/VSS traces must be routed as short, tightly coupled differential pairs directly to MOSFET drain and source pins. Sensing loops should be physically separated between channels and kept away from power loops to avoid noise coupling and false turn-off triggering.

Does MP6925GS-P require external components for basic operation?

Only three external components are mandatory: a VDD decoupling capacitor ≥1µF, a pull-up resistor on LL for light-load timing (optional if disabled), and optional 22pF capacitor on LL if left open. No external resistors are needed for V_fwd setting or gate drive bias.

What thermal derating applies to the SOIC-8 package at 85°C ambient?

With θJA = 90°C/W, maximum continuous power dissipation at T_A = 85°C is PD(MAX) = (125°C − 85°C) / 90°C/W = 0.44W. This assumes JEDEC-standard 4-layer PCB; actual derating depends on copper area and airflow per MPS AN-107 layout guidelines.

How does the turn-on blanking time affect MOSFET selection?

tB_ON = 1.1µs minimum on-time prevents shoot-through but requires MOSFETs with Qg low enough to achieve tDon < 250ns at 200kHz (5µs period). For example, a 10nF CLOAD yields tDon = 410ns max - so Qg must be ≤15nC to meet 5% cycle limit and maintain >94% efficiency.