Monolithic Power Systems Inc. MP6928AGS-P

Overview

MP6928AGS-P from Monolithic Power Systems is a dual-channel, fast-turn-off intelligent rectifier IC designed for synchronous rectification in LLC-resonant converters. It drives two N-channel MOSFETs with adaptive forward-voltage regulation (VFWD-HIGH: 32–75 mV; VFWD-LOW: 70–140 mV), ultra-low sleep-mode current (<150 µA), and reverse-current protection. It operates across 4.3V–35V VDD and supports CCM/CrCM/DCM modes in AC/DC adapters and telecom SMPS.

For engineers reviewing the MP6928AGS-P datasheet, MP6928AGS-P pinout, MP6928AGS-P application, or MP6928AGS-P equivalent, key selection criteria include turn-off total delay (35–100 ns), light-load latch-off timing (tLL = 50–100 µs), adaptive VFWD staging, SOIC-8 package thermal resistance (θJA = 90°C/W), and compatibility with 5V/12V logic-level MOSFETs.

Technical Context

The MP6928AGS-P implements dual independent channel control with separate VD1/VSS and VD2/VSS sensing inputs, enabling high-side and low-side synchronous rectification in asymmetric topologies. Its adaptive VFWD regulation uses two-stage forward-voltage thresholds to dynamically adjust gate drive voltage during conduction, minimizing conduction loss while maintaining fast transient response.

Internal protection includes under-voltage lockout (UVLO rising at 4.05 V), thermal shutdown at 160°C with 25°C hysteresis, and reverse-current detection via VDrv-Off threshold (−30 to 0 mV). Light-load mode latches off gate drivers when VG1/2 remains below 2.5 V for ≥75 µs, reducing quiescent current to <130 µA with configurable exit delay via external RLL.

Key Specifications

Pinout & Package

The MP6928AGS-P is housed in an SOIC-8 package with exposed thermal pad (not electrically connected), θJA = 90°C/W on 4-layer PCB, and MSL Level 2 moisture sensitivity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar intelligent synchronous rectifier applications.

Compared with MP6928AGS-P, MP6929 delivers lower latency and standby current but requires board rework, while SRK2001 sacrifices channel count, adaptability, and protection for cost reduction in low-complexity DCM systems.

Availability

MP6928AGS-P is available at Aetrix Electronics and suitable for AC/DC adapters, LCD & PDP TV power supplies, and telecom SMPS requiring stable component supply despite end-of-life status.

Supply support for MP6928AGS-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, including DC-DC converters, LED drivers, motor drivers, and intelligent rectifiers.

The MP69xx family targets high-efficiency LLC and resonant converter secondary-side control, emphasizing fast turn-off, adaptive VFWD, and ultra-low quiescent current for energy-critical applications.

FAQ

Is MP6928AGS-P still recommended for new designs?

No. The datasheet explicitly states "NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MP6929". MP6929 is the designated successor with improved timing, lower IQ, and updated ESD protection. MP6928AGS-P remains available for legacy production and repair, but no new design-in should use it.

What is the function of the LL pin, and how does it affect light-load behavior?

The LL pin configures light-load exit delay via an external resistor to GND. With RLL = 1 MΩ, tExit-Delay is 0.65–1.35 ms; floating disables light-load mode entirely. Pulling LL low eliminates the delay. This pin enables precise synchronization with LLC burst-mode frequency without external timing components.

Can MP6928AGS-P drive both high-side and low-side MOSFETs in the same LLC transformer secondary?

Yes. Independent VD1/VSS and VD2/VSS sensing inputs, plus separate VG1 and VG2 outputs, support simultaneous high-side and low-side synchronous rectification - for example, in center-tapped or full-bridge LLC configurations where each MOSFET senses its own drain-source voltage.

What is the maximum allowable VD voltage, and how is overvoltage protected?

The absolute maximum VD voltage is +200 V. Internal high-voltage JFET input stages provide inherent clamping, but a 1 kΩ resistor between VD and the MOSFET drain is required to limit current when VD drops below −0.7 V, preventing latch-up during fast negative transients.

How does adaptive VFWD staging improve efficiency compared to fixed-threshold controllers?

Adaptive VFWD uses two thresholds: a lower VFWD-HIGH (32–75 mV) for initial turn-on and a higher VFWD-LOW (70–140 mV) during steady conduction. This maintains strong gate drive early in conduction while reducing gate voltage later, optimizing RDS(ON) utilization and minimizing body-diode conduction time across load range.

What thermal derating applies to the SOIC-8 package at elevated ambient temperatures?

With θJA = 90°C/W, the maximum continuous power dissipation at TA = 85°C is PD(MAX) = (150°C − 85°C) / 90°C/W ≈ 0.72 W. Exceeding this causes thermal shutdown at 160°C, with recovery after 25°C hysteresis. Layout must minimize θJA via copper pour and thermal vias under the exposed pad area.