Monolithic Power Systems Inc. MP6960GS-P

Overview

MP6960GS-P from Monolithic Power Systems is a synchronous rectification controller for high-efficiency flyback converters, integrating CC/CV regulation, fast turn-off (20ns total delay), 70mV forward-drop regulation, and light-load sleep mode (<300μA). It serves as the secondary-side intelligent controller in AC/DC adapters-e.g., 15W notebook chargers-driving external MOSFETs while providing opto-coupled feedback to primary-side PWM ICs.

For engineers reviewing the MP6960GS-P datasheet, MP6960GS-P pinout, MP6960GS-P application, or MP6960GS-P equivalent, key selection criteria include its dual-loop CC/CV control architecture, SOIC8 package compatibility with 5V/12V logic-level FETs, ±0.5% 2.5V reference accuracy, and support for CCM/DCM/QR topologies in battery charging and industrial power systems.

Technical Context

The MP6960GS-P implements two independent control loops: a voltage loop using a 2.5V ±0.5% internal reference and a current loop using a 25mV ±5% reference, both processed by 1MHz-bandwidth op-amps with ORED output driving an opto-coupler. Its gate driver delivers 2A pull-down current with 1Ω impedance and regulates V_DS to ~−70mV during conduction.

It features adaptive blanking (1.6µs minimum on-time, 200ns turn-off blanking), UVLO (5.6V rising threshold), thermal shutdown (150°C), and light-load latch-off triggered by V_GS < 1.0V and V_DS < −250mV-enabling <300μA quiescent current while maintaining fast 20ns turn-off propagation under full load.

Key Specifications

Pinout & Package

MP6960GS-P is housed in an industry-standard SOIC8 package (JEDEC MS-012, variation AA) with 1.27mm pitch, 3.9mm × 4.9mm body, and exposed pad not present. Thermal resistance θ_JA = 90°C/W on 4-layer PCB.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous rectification with CC/CV control applications.

Compared with MP6960CGS-P, the MP6960GS-P trades minor reference accuracy for lower unit cost while retaining identical timing, protection, and topology support; versus SRK2001TR, it integrates full secondary-side regulation-reducing BOM count by 4–6 components but increasing IC complexity.

Availability

MP6960GS-P is available at Aetrix Electronics and suitable for USB-C adapters, industrial flyback PSUs, battery charging systems, and distributed power architectures requiring stable component supply, RoHS-compliant packaging, and long-term lifecycle support.

Supply support for MP6960GS-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP6960 belongs to MPS's Intelligent Synchronous Rectification product line, engineered specifically for high-efficiency secondary-side control in AC/DC flyback converters with integrated CC/CV regulation and ultra-low standby power.

FAQ

What is the maximum VD-to-GND voltage rating for MP6960GS-P?

The MP6960GS-P supports a VD-to-GND operating range of 4.5V to 36V, with absolute maximum rating of −0.7V to +40V. This allows direct connection to outputs up to 36V without external level-shifting, and accommodates transient spikes within the specified margin.

How does the light-load latch-off function reduce quiescent current?

When the synchronous MOSFET conduction time falls below the programmable t_LL threshold (1.3–2.6µs) for longer than t_LL-Delay (100µs), the gate driver latches off. The IC then monitors V_DS to detect body-diode conduction end, reducing active circuitry and achieving <300μA I_q.

Can MP6960GS-P drive both high-side and low-side synchronous rectifiers?

Yes-the MP6960GS-P supports both configurations. For high-side rectification, VSS connects to the MOSFET source (floating node), and VD senses drain referenced to GND. For low-side, VSS ties to GND and VD senses the switched node, leveraging its −0.7V to +40V VD-to-GND rating.

What is the purpose of the 1.6µs turn-on blanking time?

The 1.6µs blanking period prevents false turn-off during MOSFET turn-on transients. During this time, the turn-off threshold is raised to +50mV (vs. normal −30mV), ensuring reliable conduction initiation-even with fast-rising V_DS-and avoiding shoot-through in CCM operation.

How is output current set using the IFB pin?

Output current is set by sizing R_SEN so that I_OUT × R_SEN = 25mV. For example, a 3.7A output requires R_SEN = 6.76mΩ. The IFB pin compares this voltage to the internal 25mV reference; exceeding it reduces CTL current to lower primary-side duty cycle.

Does MP6960GS-P require external compensation components for the CC/CV loops?

No-both voltage and current loops use internally compensated op-amps with fixed 1MHz gain-bandwidth product. External RC networks are unnecessary; stability is ensured across all supported topologies (CCM, DCM, QR) when using recommended opto-coupler and feedback resistor values.

What MOSFET R_ON range is recommended for optimal efficiency?

MPS recommends R_ON ≥ 35mΩ/I_OUT (e.g., ≥7mΩ for 5A). This balances conduction loss against gate drive loss: too-low R_ON forces VG into inefficient linear region during light loads, negating R_ON benefits while increasing switching loss.