Monolithic Power Systems Inc. MP6960GS-Z

Overview

MP6960GS-Z from Monolithic Power Systems is a synchronous rectification controller for high-efficiency flyback converters, integrating CC/CV regulation, fast turn-off (20ns total delay), 70mV forward-drop regulation, and light-load sleep mode (<300μA). It operates with 8–24V VDD, supports up to 400kHz switching, and delivers precise 2.5V ±0.5% voltage reference and 25mV ±5% current reference for notebook adapter power supplies.

For engineers reviewing the MP6960GS-Z datasheet, MP6960GS-Z pinout, MP6960GS-Z application, or MP6960GS-Z equivalent, key selection criteria include its dual-loop CC/CV feedback architecture, SOIC8 package compatibility, gate drive capability for 12V/5V logic-level MOSFETs, and support for CCM/DCM/QR topologies in energy-sensitive AC-DC adapters.

Technical Context

The MP6960GS-Z implements two independent control loops: one compares VFB against a 2.5V bandgap reference to regulate output voltage, the other compares IFB against a 25mV current reference to enforce constant-current limits. Both loops drive a common ORED opamp output that modulates CTL to adjust primary-side PWM via opto-coupler feedback.

Its synchronous rectifier core uses real-time VD–VSS sensing to detect MOSFET body-diode conduction, then applies adaptive gate drive-turning on when VDS falls below –70mV and turning off within 20ns of crossing –30mV-with blanking intervals (1.6µs min-on, 200ns post-turn-off) preventing shoot-through in QR and DCM operation.

Key Specifications

Pinout & Package

MP6960GS-Z is housed in an industry-standard SOIC8 package (JEDEC MS-012, variation AA), with 1.27mm pitch, 3.9mm × 4.9mm body, and exposed thermal pad not present. Pin 1 is marked with a notch or dot; device orientation follows standard SOIC conventions.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous rectification with CC/CV control applications.

Compared with NCP4306DR2G and AP4313KTR-G1, MP6960GS-Z uniquely integrates precise 2.5V/25mV references, 20ns turn-off, and <300μA light-load mode-enabling single-chip CC/CV compliance in space- and efficiency-critical 15–65W adapters without external components.

Availability

MP6960GS-Z is available at Aetrix Electronics and suitable for laptop AC adapters, USB PD fast chargers, industrial 24V DC power modules, and medical-grade flyback supplies requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for MP6960GS-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MP6960 belongs to MPS's secondary-side intelligent controller product line, engineered specifically for high-efficiency, low-standby-power AC-DC flyback converters targeting consumer, computing, and industrial power applications.

FAQ

What is the minimum recommended MOSFET R_DS(on) for MP6960GS-Z in a 5A application?

The MP6960GS-Z regulates VDS at approximately –70mV during conduction. To ensure the MOSFET remains fully enhanced and avoids excessive gate drive loss, select R_DS(on) ≥ 35 mΩ for a 5A output. This value derives from V_fwd = I_OUT × R_DS(on), ensuring sufficient voltage headroom for reliable gate control while balancing conduction and switching losses.

Can MP6960GS-Z operate in quasi-resonant (QR) flyback topologies?

Yes. The MP6960GS-Z explicitly supports QR operation via its adaptive blanking timers (1.6µs min-on, 200ns post-turn-off), 20ns turn-off delay, and ability to detect zero-current crossing through VDS polarity reversal. Its block diagram confirms dedicated logic for QR waveform interpretation, and Figure 5 in the datasheet shows validated QR flyback waveforms.

How does the light-load latch-off function reduce power consumption?

The light-load mode activates when the MOSFET conduction period falls below 1.3–2.6µs for longer than 100µs. Once engaged, the gate driver latches off, eliminating dynamic gate charge loss and reducing total quiescent current to <300μA. This meets Energy Star 1W standby requirements without requiring auxiliary bias windings or external disable circuitry.

What is the purpose of separate VSS and GND pins?

VSS serves as the reference for high-voltage VD sensing and synchronous rectifier logic, tied directly to the MOSFET source to enable accurate VDS measurement. GND is the low-noise analog ground for VFB, IFB, and internal references. Separating them prevents switching noise from the power path from corrupting feedback signals, improving regulation accuracy and stability.

Does MP6960GS-Z require an external voltage reference for CV regulation?

No. The MP6960GS-Z integrates a trimmed 2.5V ±0.5% bandgap voltage reference internally. VFB compares the resistor-divider output directly to this on-chip reference, eliminating the need for external references or trimming components. This simplifies layout, reduces BOM count, and improves temperature stability over discrete solutions.

What is the maximum allowable VD-to-GND voltage for continuous operation?

The absolute maximum VD-to-GND rating is +40V, but the recommended operating condition specifies 4.5V to 36V. For reliable continuous operation, VD should remain ≤36V. Exceeding this risks exceeding junction temperature limits under load due to increased power dissipation in the CC/CV controller section, even if within absolute max ratings.

How does the ORED output of the two opamps improve system reliability?

The ORED CTL output ensures that either CV or CC loop violation triggers immediate opto-coupler current increase, forcing primary-side PWM reduction. This prevents simultaneous voltage overshoot and current overload-critical in battery charging where CV-to-CC handoff must be seamless and fault-tolerant without software intervention or external arbitration logic.