Monolithic Power Systems Inc. MP8757GL-P

Overview

MP8757GL-P from Monolithic Power Systems is a fully integrated, high-frequency synchronous step-down converter delivering 7A continuous output current across a 5V–18V input range. It employs Constant-On-Time (COT) control for fast transient response and seamless PFM mode transition at light load, features internal 25mΩ/12mΩ MOSFETs, 500kHz switching frequency, and integrated power-good signaling with OCP/OVP/UVP/thermal shutdown protection - deployed in laptop VRMs and server point-of-load regulation.

For engineers reviewing the MP8757GL-P datasheet, MP8757GL-P pinout, MP8757GL-P application, or MP8757GL-P equivalent, key selection considerations include its QFN-21 (3mm×4mm) package, adjustable 0.604V–5.5V output, 4.5V UVLO threshold, internal soft-start timing (1.95ms typ), and bootstrap-driven high-side gate drive requiring external BST capacitor placement.

Technical Context

The MP8757GL-P implements a proprietary COT control architecture with internal ramp compensation, enabling stable operation with ceramic output capacitors without external ESR dependency. Its valley-current overcurrent protection uses low-side R_DS(ON) sensing, while dynamic regulation during OVP events actively discharges the output via the low-side FET as a –1A current sink.

Thermal management relies on non-latching 150°C junction shutdown with 25°C hysteresis, and the open-drain PG signal asserts after FB reaches 95% V_REF with 450μs delay. The EN pin supports adjustable UVLO via external resistor divider, and output discharge is enabled via an internal 6Ω MOSFET when disabled or faulted.

Key Specifications

Pinout & Package

MP8757GL-P is housed in a thermally enhanced QFN-21 package (3mm × 4mm, 0.5mm pitch) with exposed thermal pad (pins 10, 11, 12, 19, 20, 21). Pin 1 is BST; pin 13 is open-drain PG; pin 14 is FB; pin 17 is digital EN; and pins 19–21 are VIN/PGND connections requiring multiple vias for low-impedance routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck converter applications.

Compared with RTQ2132BGQW and TPS546B24A, MP8757GL-P offers the best balance of integration (internal BST, discharge, soft-start), compact footprint (QFN-21), and light-load efficiency (PFM mode) for cost-sensitive, space-constrained computing applications-without sacrificing reliability or thermal performance.

Availability

MP8757GL-P is available at Aetrix Electronics and suitable for laptop computer power delivery, server point-of-load conversion, and networking system auxiliary rails requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for MP8757GL-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and mixed-signal ICs for power management, motion control, and automotive applications.

The MP8757 belongs to MPS's high-current synchronous buck converter product line, designed specifically for compact, high-efficiency DC/DC conversion in portable computing and infrastructure equipment where thermal density and layout simplicity are critical.

FAQ

What is the minimum recommended output capacitance for stable operation with MP8757GL-P?

The MP8757GL-P is optimized for ceramic output capacitors and requires ≥22μF total effective capacitance with ≤5mΩ ESL. Typical designs use two 10μF X7R 0805 ceramics in parallel. Lower values may cause instability in CCM mode unless external ramp compensation is added per Equation 5 in the datasheet.

Can MP8757GL-P operate with an input voltage below 5V?

No - the absolute minimum operating input voltage is 5V per the Recommended Operating Conditions table. Although the UVLO threshold is 4.5V, the device cannot sustain regulation or deliver rated current below 5V due to internal gate drive limitations and reduced headroom for the high-side FET.

How does the internal output discharge function behave during thermal shutdown?

During thermal shutdown, the MP8757GL-P disables both MOSFETs and activates the internal 6Ω discharge FET between VOUT and PGND. This discharges the output capacitor within ~5ms (dependent on C_OUT value), preventing latch-up or damage to downstream components when cooling resumes.

Is the PG (power-good) signal asserted during soft-start?

No - the PG signal remains low until FB voltage exceeds 95% of V_REF (574mV) and remains high for ≥450μs. Since soft-start ramps V_REF over ~1.95ms, PG asserts only after output regulation is confirmed - ensuring downstream logic receives a valid "rail ready" signal.

What is the maximum allowable BST capacitor voltage rating?

The BST pin sees voltage up to V_IN + 5.5V per Absolute Maximum Ratings. For 18V max input, a 25V-rated 0.1μF X7R ceramic capacitor is recommended. Derating to 50% voltage rating (i.e., 35V+ for 18V_IN) improves long-term reliability under surge conditions.

Does MP8757GL-P support external synchronization to a system clock?

No - the MP8757GL-P uses fixed-frequency COT control and does not provide SYNC or CLKIN pins. Its switching frequency varies ±20% with input/output conditions but remains centered at 500kHz; external synchronization is not supported in this generation.

How is overvoltage protection triggered and cleared?

OVP triggers when FB exceeds 115% V_REF, initiating dynamic regulation (LS-FET sinks –1A). If FB rises beyond 130% V_REF, the part latches off. Recovery requires EN toggling low-high or full VIN power cycle - no automatic reset occurs after fault clearance.