Monolithic Power Systems Inc. MP8758HGL-P

Overview

MP8758HGL-P from Monolithic Power Systems is a high-current, synchronous step-down DC/DC converter delivering 10A continuous output with 4.5V–22V input range, 0.604V–5.5V adjustable output, and proprietary constant-on-time (COT) control for fast transient response. It integrates low-R_DS(ON) MOSFETs (25mΩ HS / 9mΩ LS), supports PFM/PWM mode selection via MODE pin, and features hiccup-mode over-current protection and auto-retry thermal shutdown at 150°C. Used in flat-panel TV power rails requiring stable 1.2V/10A supplies.

For engineers reviewing the MP8758HGL-P datasheet, MP8758HGL-P pinout, MP8758HGL-P application, or MP8758HGL-P equivalent, key selection criteria include its 500kHz switching frequency, open-drain power-good signal timing (800μs delay), valley-current OCP threshold (10–12A), thermal hysteresis (25°C), and QFN-21 package thermal resistance (θ_JA = 50°C/W).

Technical Context

The MP8758HGL-P employs a constant-on-time (COT) control architecture that dynamically adjusts on-time based on input and output voltages to maintain ~500kHz switching frequency across operating conditions. Its valley-current sensing uses the low-side MOSFET's R_DS(ON) for cycle-by-cycle over-current protection, triggering hiccup mode upon sustained overload.

It integrates dual MOSFETs, internal 5V LDO (VCC), soft-start (2.9ms), output discharge, and power-good monitoring with 95–105% V_REF window and 800μs assertion delay. Mode selection (PFM vs forced PWM) is implemented via external voltage on the MODE pin, with internal 1MΩ pull-up enabling default PFM operation.

Key Specifications

Pinout & Package

MP8758HGL-P is housed in a thermally enhanced QFN-21 package (3mm × 4mm, 0.5mm pitch) with exposed thermal pad (Pins 10, 11, 20, 21) for efficient heat dissipation. The package supports reflow soldering per JEDEC J-STD-020 and achieves θ_JA = 50°C/W on 4-layer PCB.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-current synchronous buck converter applications.

Compared with RTQ2132BGQW and TPS546D24RSAR, MP8758HGL-P provides superior light-load efficiency via PFM mode, integrated hiccup OCP for robust short-circuit handling, and a fully monolithic 10A solution in a smaller 3mm×4mm footprint-making it optimal for space-constrained, cost-sensitive consumer power designs.

Availability

MP8758HGL-P is available at Aetrix Electronics and suitable for flat-panel television power rails, multi-function printer logic supplies, and distributed power systems requiring stable component supply with guaranteed long-term availability.

Supply support for MP8758HGL-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with over two decades of expertise in DC/DC conversion, motor drivers, and LED lighting controllers.

The MP8758HGL-P belongs to MPS's high-current monolithic buck converter product line, designed specifically for consumer and industrial applications demanding compact, efficient, and robust 10A power delivery without external MOSFETs or complex compensation.

FAQ

What is the recommended input capacitor configuration for MP8758HGL-P?

Use a minimum 22µF X7R/X5R ceramic capacitor placed within 3mm of VIN and PGND pins, supplemented by a 100nF high-frequency ceramic in parallel. Total effective capacitance should exceed 30µF with ESL < 1nH; avoid tantalum or aluminum electrolytics due to ESR instability under ripple current.

How does the hiccup-mode over-current protection behave during a sustained short circuit?

Upon detecting valley current >12A, MP8758HGL-P disables switching, discharges the soft-start capacitor, waits for thermal recovery (cooling 25°C below 150°C), then attempts automatic restart. This cycle repeats every ~250ms, limiting average short-circuit power dissipation to <1.5W and preventing thermal runaway.

Can MP8758HGL-P operate with ceramic output capacitors without external ramp compensation?

Yes-the device includes an internal ramp compensator enabling stable operation with low-ESR ceramic output capacitors down to 22µF. External ramp (R4/C4) is only needed if instability persists in PWM mode, typically with very high-value (>100µF) or ultra-low-ESR (<5mΩ) ceramics.

What is the maximum allowable voltage on the EN pin, and how is it protected?

The EN pin has an internal 12V Zener clamp; absolute maximum voltage is 12V. When pulled up directly to VIN >12V, a resistive divider must limit current to ≤1mA. For example, with VIN = 22V, use R_UP ≥ 100kΩ and R_DOWN = 51kΩ to ensure EN stays within 0–12V and meets 1.25V enable threshold.

How does MODE pin configuration affect light-load efficiency and output voltage ripple?

When MODE is floating or high (PFM), switching frequency drops under light load, reducing switching losses and improving efficiency to >85% at 10mA-but increases low-frequency output ripple. When MODE is pulled low (forced PWM), frequency remains fixed at ~500kHz, minimizing ripple amplitude but reducing light-load efficiency by 15–20 percentage points.

Is the exposed thermal pad (Pins 10,11,20,21) required to be soldered to PCB ground?

Yes-the exposed pad must be soldered to a solid PGND copper plane using ≥4 thermal vias (0.3mm diameter) to achieve specified θ_JA = 50°C/W. Leaving it unconnected raises junction temperature by >40°C at 10A load and risks thermal shutdown during sustained operation.

What is the purpose of the AGND pin, and how should it be routed relative to PGND?

AGND serves as the precision reference for the 604mV feedback comparator and internal bandgap. It must be connected to the same ground net as the FB resistor divider's GND node, but kept physically separate from high-current PGND traces until joined at a single star point near the input capacitor to prevent noise coupling into regulation loop.