Monolithic Power Systems Inc. MP8760GL-P
- Part No.:
- MP8760GL-P
- Manufacturer:
- Monolithic Power Systems Inc.
- Package:
- 13-VFQFN
- Datasheet:
-
MP8760GL-P.pdf
- Description:
- IC REG BUCK ADJ 6A 13QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,830
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MP8760GL-P from Monolithic Power Systems is a fully integrated, synchronous step-down DC/DC converter delivering 6A output current with 2.5V–18V input range (external 5V bias) or 4.5V–18V (internal bias), 0.611V–13V adjustable output, and proprietary Constant-On-Time (COT) control for ultrafast transient response in compact 3mm×4mm QFN-13 package. It targets high-density power rails in set-top boxes, small-cell base stations, and flat-panel displays.
For engineers reviewing the MP8760GL-P datasheet, MP8760GL-P pinout, MP8760GL-P application, or MP8760GL-P equivalent, key selection criteria include its non-latch OCP/OVP/thermal shutdown protection, programmable 200kHz–1MHz switching frequency via FREQ pin, 1% reference voltage accuracy over −40°C to +125°C, and pre-bias startup capability for reliable system power sequencing.
Technical Context
The MP8760GL-P implements adaptive COT control without an external oscillator, using input-voltage feed-forward through the FREQ pin to maintain near-constant switching frequency across input variations. Its internal high-side (28 mΩ) and low-side (16 mΩ) MOSFETs enable high-efficiency operation in both CCM and skip-mode DCM.
It integrates a 4.8V internal LDO (VCC), open-drain power-good (PG) with 2.5ms delay and 91% rising threshold, soft-start controlled by external capacitor, and dual-level over-current protection: valley current limit (6.5–8.5A) and negative current limit (−4A to −1A), all implemented with non-latch behavior.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V–18V with external 5V VCC bias; enables ultra-low VIN operation in battery-backed systems. |
| Output Current | 6A continuous; supports high-power SoC or FPGA core rails without external current sharing. |
| Reference Voltage | 611 mV ±9 mV over −40°C to +125°C; ensures ≤1% output regulation error across full junction temperature range. |
| Switching Frequency | 200 kHz–1 MHz, resistor-programmable via FREQ pin; balances efficiency vs. LC size-e.g., 500 kHz allows <1 µH inductors. |
| RDS(ON) | High-side: 28 mΩ, low-side: 16 mΩ at TJ = 25°C; minimizes conduction loss and thermal rise at full load. |
| Protection Features | Non-latch OCP (valley & negative), OVP (117–123% VFB), thermal shutdown at 150°C; enables automatic recovery without system reset. |
| Soft-Start | Externally programmable via SS pin (20 µA charging current); prevents inrush current into large output capacitors during power-up. |
Pinout & Package
MP8760GL-P is housed in a thermally enhanced 3mm×4mm QFN-13 package with exposed PGND pad for optimal heat dissipation and EMI control. Pin numbering follows standard top-view orientation with pin 1 at top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (EN) | Enable control input | Digital ON/OFF control; internal UVLO threshold <4.1V; resistor divider on EN sets custom startup voltage. |
| 2 (FREQ) | Frequency programming | Resistor-to-IN sets switching frequency with line feed-forward; stabilizes fSW across VIN variation. |
| 3 (FB) | Feedback sensing | Monitors output via resistor divider; enables precise VOUT setting and OVP detection at 117–123% VREF. |
| 4 (SS) | Soft-start timing | External capacitor controls ramp rate of output voltage; prevents overshoot and inrush into pre-biased loads. |
| 5 (AGND) | Analog ground reference | Separate ground for control circuitry; must be isolated from PGND to avoid noise coupling into feedback path. |
| 6 (PG) | Power-good indicator | Open-drain output signals valid regulation (≥91% VFB) after 2.5ms delay; critical for system power sequencing. |
| 7 (VCC) | Internal LDO output | 4.8V regulated supply for gate drivers and logic; disabled when external 5V bias applied, extending low-VIN capability. |
| 8 (BST) | Bootstrap supply | Capacitor between BST and SW generates floating gate drive for high-side MOSFET; enables 100% duty cycle capability. |
| 9,10 (PGND) | Power ground return | High-current return path for output inductor and MOSFETs; requires wide copper pour and multiple vias to minimize IR drop. |
| 11,12 (SW) | Switch node | Connects to inductor and BST capacitor; experiences fast dV/dt edges-requires tight layout to reduce EMI and shoot-through risk. |
| 13 (IN) | Main input supply | Accepts 2.5V–18V (with external bias) or 4.5V–18V (internal bias); requires local ≥10µF ceramic decoupling close to pin. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive COT control | Eliminates external compensation network; achieves <10 µs load transient response without loop tuning effort. |
| Proprietary switching-loss reduction | Optimizes dead-time and gate drive timing to suppress shoot-through and body-diode conduction losses. |
| Pre-bias startup | Monotonically ramps output even when VOUT is pre-charged; prevents reverse current flow into powered-down downstream circuits. |
| Programmable soft-start time | Adjustable from ~1 ms to >100 ms via SS capacitor; avoids current-limit triggering during bulk capacitor charging. |
| Non-latch fault protection | OCP, OVP, and thermal shutdown auto-recover after fault clears-no manual reset or power cycle required. |
Applications
| Set-Top Box Power Rails | Small-Cell Base Station RFIC Supply |
|---|---|
|
Use Scenario: Providing clean, tightly regulated 1.2V/3A core voltage to SoC in consumer STB with space-constrained PCB. IC Role / Device Role / Timing Role: Primary synchronous buck regulator managing dynamic load steps up to 3A/µs during video decode bursts. Use Value: Adaptive COT delivers <15 mV output deviation under 2A step load, eliminating need for large output capacitance. |
Use Scenario: Generating 3.3V/4A supply for LTE transceiver IC in outdoor small-cell unit operating from 12V PoE input. IC Role / Device Role / Timing Role: High-efficiency intermediate bus converter with thermal shutdown safeguarding against enclosure overheating. Use Value: 150°C thermal shutdown with 25°C hysteresis prevents sustained overtemperature operation while enabling rapid recovery. |
| Flat-Panel Display Logic Board | Distributed Power System Intermediate Bus |
|
Use Scenario: Delivering 5V/6A to display timing controller and interface ICs on thin-bezel LCD panel with strict EMI limits. IC Role / Device Role / Timing Role: Compact, high-frequency (800 kHz) buck converter minimizing inductor footprint and radiated emissions. Use Value: Programmable 200kHz–1MHz fSW allows EMI filtering optimization-e.g., 800 kHz avoids AM radio band interference. |
Use Scenario: Stepping down 12V intermediate bus to 1.8V/5A for ASIC cluster in industrial automation controller with long-term reliability requirements. IC Role / Device Role / Timing Role: Robust point-of-load regulator with non-latch OCP protecting against shorted daughterboards during field maintenance. Use Value: Valley-current OCP (6.5–8.5A) and negative-current limit (−4A to −1A) prevent inductor saturation and MOSFET avalanche failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2236 | 16-pin QFN-3×4mm, higher efficiency at light load due to improved DCM control, 5A rating vs. 6A | Preferred for new designs per MP8760 datasheet; better suited for always-on IoT nodes requiring <100 µA quiescent current | Select MP2236 when upgrading legacy MP8760 designs-pinout differs, requires layout revision but gains RoHS-compliant thermal performance |
| MPQ8633BGLE | Automotive-grade AEC-Q100 qualified, 6A rating, integrated PMBus interface, 2.7V–18V input | Required for automotive infotainment or ADAS subsystems needing functional safety diagnostics and temperature telemetry | Choose MPQ8633BGLE only if AEC-Q100 qualification and digital monitoring are mandatory-adds cost and complexity over MP8760GL-P |
Compared with MP8760GL-P, MP2236 offers superior light-load efficiency and updated thermal design but reduces max output current to 5A, while MPQ8633BGLE adds automotive qualification and telemetry at the expense of analog simplicity and BOM cost.
Availability
MP8760GL-P is available at Aetrix Electronics and suitable for set-top box power management, small-cell base station RFIC supplies, and flat-panel display logic board applications requiring stable component supply and long-term obsolescence planning.
Supply support for MP8760GL-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with over two decades of leadership in DC/DC conversion, motor drivers, and LED lighting controllers.
The MP8760 belongs to MPS's high-current synchronous buck converter product line, engineered for space-constrained, high-efficiency power delivery in consumer, telecom, and industrial equipment where thermal density and transient response are critical.
FAQ
What is the maximum recommended input voltage for MP8760GL-P?
The absolute maximum input voltage is 21V, but the recommended operating range is 4.5V to 18V with internal bias or 2.5V to 18V with external 5V VCC bias. Sustained operation above 18V risks exceeding SOA limits of internal MOSFETs and may trigger overvoltage protection on the VCC LDO.
Can MP8760GL-P start up into a pre-biased output?
Yes-MP8760GL-P supports monotonic pre-bias startup. When the FB voltage exceeds the SS capacitor voltage at power-on, both high-side and low-side switches remain off until the SS voltage rises above the sensed output, preventing reverse current and ensuring controlled ramp-up.
How does the FREQ pin set switching frequency?
The FREQ pin connects via resistor (RFREQ) to IN, feeding input voltage into a one-shot timer that determines ON-time. Frequency is calculated as fSW ≈ 6.1 × RFREQ(kΩ) × VIN(V) / 106 kHz, with typical range 200kHz–1MHz; line feed-forward maintains stability across VIN variation.
What is the purpose of the AGND and PGND separation?
AGND serves as the quiet reference for feedback, soft-start, and control circuitry; PGND carries high di/dt switch currents. Separating them prevents noise coupling into the FB path, which could cause regulation instability or false OVP triggering-layout best practice requires single-point connection near the IC.
Does MP8760GL-P support external synchronization?
No-MP8760GL-P lacks an external sync input. It relies solely on its internal adaptive COT architecture with resistor-programmed frequency. For synchronized multi-rail systems, designers must use frequency-select resistors to align switching frequencies or select alternatives like MPQ8633BGLE with PMBus clock sync capability.
What is the minimum output voltage achievable with MP8760GL-P?
The minimum regulated output voltage is 0.611V, set by the internal 611 mV reference voltage. This is achieved using a resistor divider where R1 = 0 Ω and R2 is selected to scale FB to exactly VREF; lower outputs require external reference injection, which is not supported.
How does the power-good (PG) signal behave during undervoltage events?
PG goes low when FB falls below 80% of VREF (e.g., 489 mV for 0.611V reference) or rises above 120% VREF, with a 2.5ms delay on rising edge only. During VCC UVLO (<3.4V), PG is actively pulled low regardless of FB state, providing fail-safe indication of regulator disablement.
MP8760GL-P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 13-VFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 18V
- Voltage - Output (Min/Fixed):
- 0.611V
- Voltage - Output (Max):
- 13V
- Current - Output:
- 6A
- Frequency - Switching:
- 200kHz ~ 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 13-QFN (3x4)
MP8760GL-P FAQ
1.How can I place an order for MP8760GL-P through Aetrix?
Please submit a Request for Quotation (RFQ) for MP8760GL-P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MP8760GL-P reliable?
The price and inventory of MP8760GL-P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MP8760GL-P is usually 5 days.
3.What payment methods are accepted for MP8760GL-P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MP8760GL-P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MP8760GL-P?
MP8760GL-P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MP8760GL-P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MP8760GL-P?
For technical support, including MP8760GL-P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MP8760GL-P requirements.
6.How does Aetrix verify that MP8760GL-P is sourced from the original manufacturer or authorized distributors?
All MP8760GL-P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MP8760GL-P meets industry standards.
7.What is the process for return or replacement of MP8760GL-P?
All MP8760GL-P units undergo pre-shipment inspection (PSI). If there is an issue with MP8760GL-P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MP8760GL-P part is unused and in its original packaging.
Return procedure for MP8760GL-P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MP8760GL-P Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

