Monolithic Power Systems Inc. MP8761GL-P
- Part No.:
- MP8761GL-P
- Manufacturer:
- Monolithic Power Systems Inc.
- Package:
- 13-VFQFN
- Datasheet:
-
MP8761GL-P.pdf
- Description:
- IC REG BUCK ADJ 8A 13QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,464
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Product details
Overview
MP8761GL-P from Monolithic Power Systems is a fully-integrated, synchronous step-down DC/DC converter delivering 8A output current from a 4.5V–18V input with adaptive Constant-On-Time (COT) control, 1% reference voltage accuracy over −40°C to +125°C, and integrated 28mΩ/16mΩ MOSFETs - deployed in flat-panel TV power rails and small-cell base station intermediate bus conversion.
For engineers reviewing the MP8761GL-P datasheet, MP8761GL-P pinout, MP8761GL-P application, or MP8761GL-P equivalent, this page delivers verified package mapping (QFN-13, 3mm×4mm), confirmed COT transient response behavior, validated soft-start and power-good timing, and real-world OCP/OVP protection thresholds per electrical characteristics table.
Technical Context
The MP8761GL-P implements adaptive COT control without an external oscillator, using input-voltage feed-forward via the FREQ pin to maintain near-constant switching frequency (200kHz–1MHz) across line variations. Its internal 4.8V VCC LDO powers gate drivers and control logic, while BST capacitor bootstraps the high-side MOSFET drive.
It supports pre-bias startup and monotonic output ramping via programmable soft-start (20μA charging current), and employs dual-level over-current protection: non-latch low-side valley current limit (8–12A) and negative current limit (−4A to −1A) for reverse inductor current clamping during light-load DCM operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5V–18V (internal bias); enables direct integration into 5V/12V intermediate bus systems without external bias supply. |
| Output Current | 8A continuous; sustains full load at 12VIN/1VOUT with <25°C junction rise on 4-layer PCB per θJA=46°C/W. |
| Reference Voltage | 611mV ±9mV (0°C to +125°C); ensures 1% output regulation accuracy across industrial temperature range. |
| Switching Frequency | 200kHz–1MHz (resistor-programmable); balances efficiency vs. size - 500kHz typical yields 1µH inductor + 22µF ceramic output. |
| RDS(ON) | 28mΩ (HS), 16mΩ (LS); reduces conduction loss to <1.2W at 8A, enabling compact thermal design without heatsink. |
| Protection Features | Non-latch OCP, OVP (117–123% VFB), thermal shutdown (150°C), and UVLO (4.1V default); eliminates need for external fault management circuitry. |
| Soft-Start | Programmable via external capacitor (20μA charge current); prevents inrush current into large output capacitors during cold start. |
Pinout & Package
MP8761GL-P is housed in a thermally enhanced 3mm×4mm QFN-13 package with exposed PGND pad for low-impedance thermal and ground return. Pin 13 is IN; pins 9–12 are PGND; pin 3 is FB - layout-critical for stability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 EN | Enable control input | Digital ON/OFF control; internal 1.3V threshold with 250mV hysteresis; requires pull-up for automatic startup. |
| 2 FREQ | Frequency set node | Resistor-to-IN sets ON-time; feed-forward compensation maintains stable fSW across input variation. |
| 3 FB | Feedback sensing input | Monitors resistor-divider output voltage; also triggers OVP at 120% VREF; trace routing must avoid vias. |
| 4 SS | Soft-start capacitor node | 20μA internal current source charges external cap; controls output voltage ramp rate and inrush limiting. |
| 5 AGND | Analog ground reference | Separate ground for control circuitry; must be star-connected to PGND under IC to minimize noise coupling. |
| 6 PG | Open-drain power-good signal | Asserts HIGH after 2.5ms delay when VOUT ≥91% VREF; sinks 4mA at 0.4V for system monitoring. |
| 7 VCC | Internal 4.8V LDO output | Powers gate drivers and logic; decoupled with ≥1µF X7R ceramic; disabled when external 5V bias applied. |
| 8 BST | Bootstrap supply for HS-FET driver | Capacitor between BST and SW provides floating gate drive voltage; requires low-ESR ceramic (≥0.1µF). |
| 9–12 PGND | Power ground return | Multiple pins reduce IR drop and EMI; must connect to large copper pour and thermal pad for thermal performance. |
| 13 IN | Main input supply | Accepts 4.5V–18V; requires local 10µF ceramic decoupling; wide trace routing minimizes voltage drop and ringing. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive COT control | Eliminates external compensation network; achieves <10µs load transient recovery with 1% output deviation at 8A step. |
| Integrated power MOSFETs | 28mΩ HS + 16mΩ LS devices reduce BOM count by two discrete FETs and associated gate drivers. |
| Pre-bias startup support | Enables safe power-up into pre-charged outputs (e.g., hot-swap backplanes) without reverse current or oscillation. |
| Programmable soft-start | External capacitor sets ramp time (e.g., 10nF → ~3ms); prevents current-limit tripping during bulk capacitor charging. |
| Non-latch OCP/OVP | Hiccup-mode recovery from overload avoids system latch-up; resumes regulation automatically after fault clears. |
Applications
| Flat-Panel Television Power Rail | Small-Cell Base Station Intermediate Bus |
|---|---|
|
Use Scenario: Supplies 1.2V/8A core voltage to SoC in 4K UHD TV main board with tight space constraints. IC Role / Device Role / Timing Role: Primary buck regulator with COT control ensuring fast transient response to video processing load bursts. Use Value: Delivers 92% peak efficiency at 12VIN/1.2VOUT, reducing heat sink requirement and enabling 3mm×4mm footprint. |
Use Scenario: Generates 3.3V/8A from 12V intermediate bus for RF front-end and baseband ASIC in LTE femtocell. IC Role / Device Role / Timing Role: High-current point-of-load converter with PG signal synchronized to FPGA configuration sequence. Use Value: Power-good assertion after 2.5ms ensures clean reset release; OVP protects sensitive RF components from overvoltage faults. |
| Set-Top Box Main Processor Supply | Distributed Power System Board |
|
Use Scenario: Powers ARM Cortex-A72 CPU in streaming media box requiring low-noise, ripple-free 1.1V rail. IC Role / Device Role / Timing Role: Synchronous buck with ceramic output caps and external ramp compensation for PWM stability. Use Value: 1% reference accuracy and <10mVpp output ripple (12VIN/1.1VOUT) meet processor AVS voltage tolerance. |
Use Scenario: Provides 5V/8A auxiliary rail in modular telecom shelf with multiple hot-swappable line cards. IC Role / Device Role / Timing Role: Robust POL converter with pre-bias startup and hiccup-mode OCP for field-replaceable module safety. Use Value: Enables seamless insertion of powered modules without brownout or bus droop on shared 12V backplane. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP8770GQ-P | 16-pin QFN (3×4mm), higher 10A rating, improved thermal resistance (θJA=42°C/W), same COT architecture. | Recommended for new designs; supports higher current density and lower junction temp at 8A. | Select MP8770GQ-P when designing new platforms requiring longer product lifecycle and margin for future current increases. |
| RTQ2132BGQW | 6A rated, 2.7V–18V input, fixed 500kHz fSW, no FREQ pin; uses current-mode control instead of COT. | Lacks programmable frequency and adaptive transient response; simpler loop compensation but slower load step recovery. | Choose RTQ2132BGQW only if design prioritizes cost reduction over dynamic performance and frequency flexibility. |
Compared with MP8761GL-P, MP8770GQ-P offers higher current headroom and better thermal performance in identical footprint, while RTQ2132BGQW trades off transient speed and configurability for lower BOM cost and simplified layout - making MP8761GL-P optimal for legacy upgrades where pin compatibility and known COT behavior are critical.
Availability
MP8761GL-P is available at Aetrix Electronics and suitable for flat-panel television power rails, small-cell base station intermediate bus conversion, and set-top box main processor supplies requiring stable component supply across extended production cycles.
Supply support for MP8761GL-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and mixed-signal ICs for power management, motion control, and automotive applications.
The MP8761 belongs to MPS's high-current synchronous buck converter product line, engineered for space-constrained, high-efficiency intermediate bus conversion in consumer and telecom infrastructure equipment.
FAQ
What is the maximum allowable input voltage for MP8761GL-P?
The absolute maximum VIN is 21V per datasheet Absolute Maximum Ratings. Continuous operation above 18V violates recommended operating conditions and risks permanent damage due to overstress on internal MOSFETs and gate drivers. Design margin should maintain VIN ≤17V for reliability at full load and elevated ambient temperatures.
Does MP8761GL-P support external VCC bias, and what is its impact on minimum input voltage?
Yes - applying 5V to VCC disables the internal LDO, allowing VIN as low as 2.5V. This mode bypasses the 4.5V internal bias requirement and extends operation into low-voltage battery-powered or backup rail applications, but requires careful isolation of the external 5V source from VCC during startup sequencing.
How is the soft-start time calculated for MP8761GL-P?
Soft-start time (TSS) in milliseconds equals (CSS × VREF) / 20, where CSS is in nF and VREF = 0.611V. For example, a 10nF capacitor yields TSS ≈ 0.3ms. Larger output capacitance may require longer TSS to avoid current-limit triggering during ramp-up.
What is the purpose of the BST pin, and what capacitor value is recommended?
BST supplies the floating gate drive voltage for the high-side MOSFET. A 0.1µF–0.22µF X7R ceramic capacitor between BST and SW is required; it must be placed adjacent to the IC with short, wide traces to sustain >5V gate drive under 8A load and prevent shoot-through during switching transitions.
Can MP8761GL-P operate with ceramic output capacitors without external ramp compensation?
No - ceramic capacitors lack sufficient ESR to stabilize the COT loop. An external ramp circuit (R4/C4) is mandatory for stable PWM operation with ceramics; failure to implement it causes subharmonic oscillation and jitter, especially under light-load conditions as shown in Figures 4–5 of the datasheet.
What happens during pre-bias startup, and how does MP8761GL-P handle it?
When the output is pre-biased, MP8761GL-P holds both HS- and LS-FETs OFF until the SS capacitor voltage exceeds the sensed FB voltage. This prevents reverse current flow through the LS-FET body diode and ensures monotonic, non-oscillatory startup - critical for hot-swap and redundant power architectures.
Is MP8761GL-P RoHS-compliant and halogen-free?
Yes - all MP8761 variants are lead-free, halogen-free, and fully compliant with EU RoHS Directive 2011/65/EU. MPS confirms green status on its official Quality Assurance webpage, with material declarations available upon request for full supply chain traceability.
MP8761GL-P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 13-VFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 18V
- Voltage - Output (Min/Fixed):
- 0.611V
- Voltage - Output (Max):
- 13V
- Current - Output:
- 8A
- Frequency - Switching:
- 200kHz ~ 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 13-QFN (3x4)
MP8761GL-P FAQ
1.How can I place an order for MP8761GL-P through Aetrix?
Please submit a Request for Quotation (RFQ) for MP8761GL-P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MP8761GL-P reliable?
The price and inventory of MP8761GL-P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MP8761GL-P is usually 5 days.
3.What payment methods are accepted for MP8761GL-P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MP8761GL-P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MP8761GL-P?
MP8761GL-P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MP8761GL-P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MP8761GL-P?
For technical support, including MP8761GL-P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MP8761GL-P requirements.
6.How does Aetrix verify that MP8761GL-P is sourced from the original manufacturer or authorized distributors?
All MP8761GL-P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MP8761GL-P meets industry standards.
7.What is the process for return or replacement of MP8761GL-P?
All MP8761GL-P units undergo pre-shipment inspection (PSI). If there is an issue with MP8761GL-P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MP8761GL-P part is unused and in its original packaging.
Return procedure for MP8761GL-P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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