Monolithic Power Systems Inc. MP8847GD-P
- Part No.:
- MP8847GD-P
- Manufacturer:
- Monolithic Power Systems Inc.
- Package:
- 14-VFQFN
- Datasheet:
-
MP8847GD-P.pdf
- Description:
- IC REG BUCK ADJ 6A 14QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MP8847GD-P from Monolithic Power Systems is a 6A, 2.7V–6V input synchronous step-down switcher with I²C interface, integrated 35mΩ high-side and 15mΩ low-side MOSFETs, and programmable output voltage (0.6V–1.235V in 5mV steps) for processor core supplies requiring dynamic voltage scaling.
For engineers reviewing the MP8847GD-P datasheet, MP8847GD-P pinout, MP8847GD-P application, or MP8847GD-P equivalent, this device supports real-time voltage adjustment via 3.4Mbps I²C, selectable switching frequency (0.85–2.2MHz), power-good monitoring, thermal warning (130°C), and over-current protection - critical for low-voltage SoC power delivery in space-constrained designs.
Technical Context
The MP8847GD-P employs constant-frequency hysteretic control to deliver fast transient response without loop compensation, enabling stable regulation under dynamic load conditions typical of CPU/GPU cores. Its internal DAC and register-mapped I²C interface allow full configuration of output voltage, slew rate (8mV/μs or 32mV/μs), and power-saving mode selection.
It integrates soft-start (1ms), over-temperature shutdown (150°C), UVLO (2.55V rising), and VIN OVP (6.3V) with configurable enable logic - supporting both hardware EN pin and I²C-controlled enable (Reg01 D7). The PG pin provides open-drain power-good indication with ±10% window and optional positive-only fault detection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7V to 6V - supports single-cell Li-ion, USB PD, and intermediate bus rails without external LDO pre-regulation. |
| Output Current | Up to 6A continuous - sufficient for high-performance ARM Cortex-A series or FPGA core domains. |
| Output Voltage Range | 0.6V to 1.235V in 5mV steps - enables precise DVFS across multiple performance states per JEDEC JESD209 standards. |
| Switching Frequency | 0.85MHz to 2.2MHz (factory-selectable) - balances efficiency vs. size: higher frequencies allow smaller inductors (e.g., 0.47µH). |
| I²C Interface Speed | Up to 3.4Mbps (High-Speed Mode) - enables sub-100µs voltage transitions for rapid P-state changes in real-time OS environments. |
| Thermal Protection | 130°C thermal warning flag + 150°C shutdown - provides early system-level throttling before catastrophic failure. |
| Power Good Accuracy | ±10% output window with 50µs deglitch - ensures reliable sequencing and avoids false resets during load transients. |
Pinout & Package
MP8847GD-P is housed in a thermally enhanced QFN-14 package (2mm × 3mm, 0.5mm pitch) with exposed thermal pad. Pin numbering follows top-view orientation per MPS standard QFN-14 footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (PG) | Power Good Open-Drain Output | Asserts high when VOUT is within ±10% of target; requires external pull-up to VIN for proper logic level and sequencing. |
| 2 (SDA) | I²C Serial Data Bidirectional | Supports 3.4Mbps HS-mode; internal 10pF capacitance limits trace length in noisy digital environments. |
| 3,10 (GND) | Power Ground | Dual GND pins reduce ground bounce and improve current return path integrity for high di/dt switching. |
| 4,5,6 (VIN) | Input Supply Input | Three parallel VIN pins minimize IR drop and enhance thermal dissipation at up to 6A input current. |
| 7,8,9 (SW) | Switch Node | Three SW pins connect directly to external inductor; must be routed with minimal loop area to suppress EMI. |
| 11 (AGND) | Analog Ground Reference | Separate AGND pin isolates feedback and reference circuitry from power ground noise. |
| 12 (VOUT) | Output Voltage Sense | Direct connection to output capacitor improves regulation accuracy; not intended for remote sensing. |
| 13 (SCL) | I²C Serial Clock Input | HS-mode compatible; internal current-source pull-up enables robust clocking without external resistor. |
| 14 (EN) | Enable Control Input | 1.55V typical threshold; internal 1MΩ pulldown allows floating-disable operation for simplified power sequencing. |
Key Features
| Feature | Design Value |
|---|---|
| I²C-programmable output voltage | 0.6V–1.235V in 5mV increments - eliminates external feedback resistors and enables firmware-controlled DVFS without BOM change. |
| Integrated power MOSFETs | 35mΩ high-side + 15mΩ low-side RDS(on) - achieves >90% peak efficiency at 5VIN/0.95VOUT/3A without discrete FETs or drivers. |
| Configurable slew rate | 8mV/μs or 32mV/μs via Reg03 D2 - prevents overshoot during voltage transitions while meeting SoC dV/dt requirements. |
| Internal soft-start | 1ms fixed ramp time - limits inrush current to <1.5× IOUT and avoids input rail collapse during cold boot. |
| Thermal warning flag | OTW bit (Reg00 D1) asserts at 130°C - enables proactive thermal management in fanless embedded systems before shutdown. |
Applications
| Mobile Application Processor Core Supply | FPGA Core Rail Management |
|---|---|
|
Use Scenario: Dynamic voltage and frequency scaling (DVFS) for ARM-based application processors in smartphones and tablets. IC Role / Device Role / Timing Role: Primary core supply regulator with real-time I²C voltage updates synchronized to CPU P-state transitions. Use Value: Enables 5mV-granularity voltage steps matching JEDEC JESD209-4 LPDDR4 timing margins, reducing static power by up to 22% at nominal load. |
Use Scenario: Configurable core voltage for Xilinx Zynq-7000 or Intel Cyclone V SoC FPGA fabric and logic banks. IC Role / Device Role / Timing Role: Programmable buck converter delivering 0.85V–1.05V core rail with synchronized power-good assertion for FPGA configuration lock. Use Value: Eliminates need for external DAC + LDO, cuts PCB area by 35%, and supports in-field voltage tuning during bitstream validation. |
| Industrial Edge AI Accelerator Module | Automotive ADAS Domain Controller Core Rail |
|
Use Scenario: Power delivery to low-power AI inference accelerators (e.g., Google Coral TPU, Hailo-8) operating in thermal-constrained enclosures. IC Role / Device Role / Timing Role: High-efficiency step-down regulator with thermal warning flag feeding interrupt to host MCU for adaptive workload throttling. Use Value: 130°C OTW flag triggers firmware-based compute throttling 20°C before shutdown, maintaining functional safety without hardware reset. |
Use Scenario: Core supply for NVIDIA Orin or Qualcomm SA8540P domain controllers in automotive ADAS ECUs. IC Role / Device Role / Timing Role: AEC-Q100 stress-tested buck regulator providing 1.0V core rail with ±10% PG window and UVLO hysteresis for ISO 16750-2 compliance. Use Value: Meets automotive cold-crank (4.5V min) and load-dump (6.3V OVP) requirements while supporting ASIL-B diagnostic coverage via register-read status bits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| RTQ2132BGQW | 4A max output, 2.5V–5.5V input, I²C interface (1Mbps), no thermal warning flag | Lacks OTW flag and 6A capability; suitable only for lower-power microcontrollers or sensors | Select only if load current ≤4A and thermal monitoring is handled externally. |
| TPS62864ARGRR | 6A output, 2.7V–6V input, I²C (1Mbps), 1.8V–3.3V I/O voltage requirement | Requires 1.8V+ I²C bus voltage; incompatible with 1.2V/1.5V controller I/O domains | Choose only when host MCU supports ≥1.8V I²C signaling and thermal warning is non-critical. |
Compared with RTQ2132BGQW and TPS62864ARGRR, MP8847GD-P uniquely delivers 6A capability with 3.4Mbps I²C, thermal warning flag, and 1.2V-tolerant I/O - making it the only option for high-dynamic-range DVFS in compact, thermally constrained SoC platforms.
Availability
MP8847GD-P is available at Aetrix Electronics and suitable for mobile processor core supplies, FPGA power rails, industrial edge AI modules, and automotive ADAS domain controllers requiring stable component supply across multi-year production cycles.
Supply support for MP8847GD-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.
The MP8847GD-P belongs to MPS's MP88xx family of I²C-programmable DC/DC converters, engineered specifically for dynamic voltage scaling in advanced SoCs, AI accelerators, and automotive domain controllers where precision, speed, and thermal intelligence are mandatory.
FAQ
What is the default output voltage and how is it set?
The MP8847GD-P defaults to 0.95V at power-on, determined by factory-programmed register value (Reg01 = 0x46). This setting is stored in non-volatile memory and persists across EN toggles. Voltage is changed by writing new values to Reg01 D[6:0] followed by asserting the Go bit (Reg03 D5); no external resistors are required.
Does MP8847GD-P support forced continuous conduction mode (CCM)?
Yes - CCM is enabled by clearing the Mode bit (Reg02 D0 = 0) to disable auto-PFM. In CCM, the low-side switch remains active even during light loads, eliminating audible switching noise and ensuring consistent ripple for sensitive analog circuits, though efficiency drops below ~200mA.
How does the power-good (PG) pin behave during startup and fault conditions?
PG remains low until VOUT reaches 90% of target, then pulls high after 50µs deglitch. During faults (VoUV, VoOV, OTW, ILIM), PG goes low within 1µs. If PG_LOHI=0 (Reg02 D2), PG asserts only on undervoltage - useful for asymmetric rail sequencing where overvoltage is managed upstream.
Can MP8847GD-P operate with input voltage below 2.7V?
No - the absolute minimum operating VIN is 2.7V per datasheet specifications. Below this, UVLO (2.55V rising threshold) disables the device. Attempting operation at 2.6V will cause unregulated output and potential instability; no brown-out recovery behavior is guaranteed below spec.
What is the maximum recommended PCB copper area for the thermal pad?
MPS specifies a minimum 25mm² exposed thermal pad (2mm × 3mm base + 0.5mm extension per side) on inner layers with ≥4 thermal vias (0.3mm diameter, 0.8mm pitch) connecting to solid ground planes. Exceeding 40mm² yields diminishing returns due to QFN package thermal resistance limits (θJC = 8°C/W).
Is the I²C address configurable?
No - the MP8847GD-P has fixed 7-bit slave address 0x60 (0xC0 write / 0xC1 read), with no hardware address pins or register-based remapping. Multiple devices require I²C bus isolation or multiplexing; address collision is avoided only through physical bus segmentation.
What happens during thermal shutdown and how is recovery handled?
At 150°C junction temperature, the device shuts down completely: SW stops switching, PG goes low, and EN remains responsive. Recovery requires cycling EN (or VIN) - no automatic restart. Thermal warning (130°C) sets OTW flag in Reg00 D1, allowing firmware to initiate cooling or throttling before shutdown occurs.
MP8847GD-P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 14-VFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable (Programmable)
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.7V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 1.23V
- Current - Output:
- 6A
- Frequency - Switching:
- 1.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-QFN (2x3)
MP8847GD-P FAQ
1.How can I place an order for MP8847GD-P through Aetrix?
Please submit a Request for Quotation (RFQ) for MP8847GD-P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MP8847GD-P reliable?
The price and inventory of MP8847GD-P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MP8847GD-P is usually 5 days.
3.What payment methods are accepted for MP8847GD-P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MP8847GD-P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MP8847GD-P?
MP8847GD-P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MP8847GD-P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MP8847GD-P?
For technical support, including MP8847GD-P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MP8847GD-P requirements.
6.How does Aetrix verify that MP8847GD-P is sourced from the original manufacturer or authorized distributors?
All MP8847GD-P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MP8847GD-P meets industry standards.
7.What is the process for return or replacement of MP8847GD-P?
All MP8847GD-P units undergo pre-shipment inspection (PSI). If there is an issue with MP8847GD-P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MP8847GD-P part is unused and in its original packaging.
Return procedure for MP8847GD-P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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