Monolithic Power Systems Inc. MP8867GLE-Z
- Part No.:
- MP8867GLE-Z
- Manufacturer:
- Monolithic Power Systems Inc.
- Package:
- 14-PowerVFQFN
- Datasheet:
-
MP8867GLE-Z.pdf
- Description:
- IC REG BUCK PROG 8A 14QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MP8867GLE-Z from Monolithic Power Systems is a high-frequency, synchronous step-down DC/DC converter with I²C programmability, delivering up to 8A output current across a 4.5V–17V input range. It features 0.6V–1.87V I²C-adjustable output voltage in 10mV steps, 1% reference accuracy, and integrated over-voltage, over-current hiccup, and thermal shutdown protections. Used in FPGA core supplies where dynamic voltage scaling and precise rail sequencing are required.
For engineers reviewing the MP8867GLE-Z datasheet, MP8867GLE-Z pinout, MP8867GLE-Z application, or MP8867GLE-Z equivalent, key selection considerations include I²C-configurable soft-start timing, external clock synchronization (200kHz–2MHz), open-drain power-good signaling, and QFN-14 (3×4mm) thermal performance with θJA = 48°C/W.
Technical Context
The MP8867GLE-Z implements current-mode control with internal high-side (30mΩ) and low-side (15mΩ) MOSFETs, enabling fast transient response and stable loop compensation without external compensation components. Its I²C interface controls not only output voltage but also switching frequency, power-save mode (PSM/FS), and voltage-slew rate-enabling dynamic V/f scaling in processor cores.
Three operating modes-CCM (default), AAM for light-load efficiency, and DCM for ultra-light loads-are selected via register bit MODE[0]. The internal 5V LDO (VCC) powers all logic and analog blocks, regulated from VIN across the full input range, with mandatory 0.47µF ceramic decoupling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output current | 8A continuous - supports FPGA/ASIC core rails with tight load-step requirements. |
| Input voltage range | 4.5V to 17V - compatible with 5V, 12V, and intermediate industrial bus voltages. |
| Output voltage range | 0.6V to 1.87V in 10mV steps - enables precise I²C-driven DVFS for SoCs and FPGAs. |
| Reference accuracy | ±1% at TJ = 25°C - ensures ±12mV error at 1.2V output, critical for sub-1V logic domains. |
| Switching frequency | Programmable 400–570kHz (typ.) - adjustable via I²C or synchronized externally from 200kHz–2MHz. |
| Thermal shutdown | 160°C with 20°C hysteresis - protects against sustained overload or poor PCB thermal design. |
| Power good delay | 100–160μs - provides deterministic system reset timing after output regulation is achieved. |
Pinout & Package
MP8867GLE-Z is housed in a thermally enhanced QFN-14 package (3mm × 4mm, 0.5mm pitch) with exposed thermal pad. Pin 14 (AGND) and Pin 8 (PGND) must be connected separately to the system ground plane using multiple vias to minimize noise coupling and ensure stable feedback operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BST (Pin 1) | Bootstrap supply | Connects external capacitor between SW and BST to generate floating gate drive for high-side MOSFET; requires UVLO monitoring at 2.2V. |
| SW (Pin 2) | Power switch node | High-current switching node; must use wide PCB trace and low-inductance layout to minimize EMI and voltage spikes. |
| SCL/SDA (Pins 3,4) | I²C interface | Supports standard/fast-mode I²C (up to 3.4MHz); SDAH/SCLH pins enable level-shifting for 1.8V–5V bus compatibility. |
| EN/SYNC (Pin 5) | Enable & sync input | Internal 5.4µA pull-up enables auto-start; accepts external clock (200kHz–2MHz) for EMI reduction via frequency dithering. |
| A0 (Pin 6) | I²C address select | Two-device addressing: float/VCC = 0x60, GND = 0x61 - enables dual-rail coordination on same I²C bus. |
| PG (Pin 7) | Power-good indicator | Open-drain output asserts high after 100µs when VFB > 90% VREF; pulls low immediately during UVLO/OTP. |
| PGND (Pin 8) | Power ground reference | Return path for output current and FB sensing; must be isolated from AGND until single-point star connection. |
| VIN (Pin 9) | Main input supply | 4.5V–17V input; requires local 10µF+ ceramic decoupling close to pin to suppress high-frequency ripple. |
| VOUT (Pin 10) | Output voltage sense | Direct connection to load terminal enables remote sensing; eliminates IR drop errors in high-current paths. |
| FB (Pin 11) | Feedback input | Connects to resistor divider tap; used only in non-I²C fallback mode; disabled when I²C control is active. |
| SS (Pin 12) | Soft-start timing | 10µA internal current charges external capacitor; sets monotonic ramp time per Equation (1) in datasheet. |
| VCC (Pin 13) | Internal LDO output | 5V regulated supply for internal circuitry; requires 0.47µF ceramic capacitor to stabilize under load transients. |
| AGND (Pin 14) | Analog ground | Reference for error amplifier and I²C logic; must connect to system ground only at one point near PGND. |
Key Features
| Feature | Design Value |
|---|---|
| I²C-programmable slew rate | Controls dv/dt of output voltage during V/f transitions-prevents overshoot during dynamic core scaling. |
| Hiccup-mode OCP | Reduces average short-circuit current during output faults, limiting junction temperature rise and enabling safe auto-recovery. |
| Pre-bias start-up | Monotonically ramps output even when load is pre-charged-essential for hot-swap and multi-rail sequencing systems. |
| Integrated bootstrap diode | Eliminates external bootstrap diode; internal charge pump maintains BST voltage ≥2.2V for reliable HS-FET turn-on. |
| OTP and OCP status reporting | I²C register bits flag hiccup events and thermal faults-enables firmware-level fault logging without external monitoring. |
Applications
| FPGA Core Supply | ASIC I/O Bank Supply |
|---|---|
Use Scenario: Powering Xilinx Kintex or Intel Stratix FPGA core logic operating at 0.85V–1.2V with dynamic voltage/frequency scaling. IC Role / Device Role / Timing Role: Primary step-down regulator with I²C-controlled output voltage and soft-start timing, synchronized to system clock for EMI management. Use Value: Enables real-time DVFS via I²C writes, reducing dynamic power by up to 35% during low-compute intervals while maintaining <±1% output regulation. | Use Scenario: Delivering 1.8V or 2.5V to ASIC I/O banks requiring clean, sequenced power with PG confirmation before configuration. IC Role / Device Role / Timing Role: Secondary buck converter configured via I²C to match I/O voltage requirements; PG signal gates FPGA configuration state machine. Use Value: Eliminates need for external voltage supervisors and discrete sequencing ICs-reduces BOM count and board area by 30%. |
| Distributed Telecom Power | Industrial CPU Module Supply |
Use Scenario: Point-of-load conversion in 48V intermediate bus architectures feeding 3.3V/5V subsystems in base station radios. IC Role / Device Role / Timing Role: High-efficiency POL regulator with external clock sync to avoid beat frequencies with adjacent RF circuits. Use Value: Achieves >92% peak efficiency at 5A/5V, and 200kHz–2MHz sync range allows alignment with master timing source to suppress conducted EMI. | Use Scenario: Powering ARM-based industrial CPUs (e.g., NXP i.MX8) requiring 1.0V core, 1.1V GPU, and 3.3V I/O rails with coordinated startup. IC Role / Device Role / Timing Role: Configurable buck controller supporting multi-phase expansion via I²C address selection (A0 pin). Use Value: Dual MP8867GLE-Z units (0x60/0x61) on same bus enable synchronized soft-start and rail tracking-ensuring <100ns inter-rail skew. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP8859GQ-Z | 6A output, 2.7V–18V input, no I²C interface - uses resistor-based FB network only. | Lacks programmable slew rate, soft-start, and real-time voltage adjustment; suitable for fixed-output designs. | Select when I²C control is unnecessary and cost sensitivity outweighs configurability needs. |
| TPS548D22RTQR | 8A, 4.5V–18V, PMBus 1.3 interface, integrated MOSFETs, 0.6V–3.6V output range. | Supports telemetry (VIN/VOUT/IOUT/temperature), more complex command set, larger 20-pin QFN package. | Choose for systems requiring comprehensive power telemetry and PMBus ecosystem integration. |
Compared with MP8867GLE-Z, MP8859GQ-Z trades I²C flexibility for lower BOM cost and simpler layout, while TPS548D22RTQR adds telemetry and broader output range at the expense of higher design complexity and footprint.
Availability
MP8867GLE-Z is available at Aetrix Electronics and suitable for FPGA-based systems, ASIC power delivery, and distributed telecom power applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for MP8867GLE-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, headquartered in Kirkland, Washington, with global design and support operations.
The MP8867 belongs to MPS's high-current, digitally configurable DC/DC converter product line, designed specifically for dynamic voltage scaling in FPGA, ASIC, and multicore processor applications where precision, efficiency, and programmability are critical.
FAQ
What is the minimum recommended soft-start capacitor value for MP8867GLE-Z?
The soft-start capacitor (SS pin) is charged by a 10µA internal current source. For a typical 10ms ramp time at 1.2V output, a 83nF capacitor is calculated using CSS = (TSS × 10µA) / VREF. A 100nF X7R ceramic capacitor is recommended to accommodate tolerance and temperature drift, placed within 2mm of the SS pin with short traces to AGND.
Can MP8867GLE-Z operate without I²C communication after initial configuration?
Yes. After power-up, MP8867GLE-Z defaults to FB-resistor control if no I²C activity is detected within ~100ms. The device retains its last programmed output voltage, frequency, and mode settings in volatile registers but reverts to analog feedback loop operation-ensuring robustness in systems with intermittent I²C bus access.
How does the MP8867GLE-Z handle output over-voltage conditions?
When FB or VOUT exceeds 120% of the reference voltage, MP8867GLE-Z activates linear discharge mode using an internal 35Ω resistor between VOUT and GND. This limits over-voltage to ≤127% VREF and holds it until VOUT drops below 105% VREF, at which point normal PWM operation resumes-no latch-off or manual reset required.
Is EN/SYNC pin 5V-tolerant when used for external clock synchronization?
No. EN/SYNC has an internal 5.7V Zener clamp, so applying >5.5V directly risks exceeding the 100µA absolute maximum current rating. For 12V clock sources, a ≥63kΩ pull-up resistor to VIN is required; for direct 3.3V/5V clocks, no series resistor is needed, and the pin safely accepts 200kHz–2MHz square waves with 50% duty cycle.
What is the purpose of separating PGND and AGND pins on the QFN-14 package?
PGND carries high di/dt return currents from the power switches, while AGND references sensitive analog circuits (error amplifier, I²C logic, DAC). Separating them prevents ground bounce from corrupting feedback accuracy or causing I²C communication errors. They must join at a single point near the input capacitor to maintain low-impedance return paths without creating ground loops.
Does MP8867GLE-Z support pre-biased output start-up, and how is it implemented?
Yes. During start-up with a pre-biased output, the internal SS capacitor charges until its voltage exceeds the sensed VOUT at FB/VOUT pin. Only then does the controller begin switching, ramping output monotonically from the pre-bias level. This avoids reverse current flow into the output capacitor and ensures glitch-free initialization in hot-swap or multi-rail systems.
What thermal derating applies to the 8A output rating in the QFN-14 package?
The 8A rating assumes θJA = 48°C/W on a 4-layer PCB with 2oz copper and thermal vias under the exposed pad. At ambient temperatures above 60°C or with reduced copper area, output current must be derated linearly: IOUT = 8A × (1 − (TA − 60)/65). At 100°C ambient, max continuous current drops to ~5.1A to maintain TJ ≤ 125°C.
MP8867GLE-Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 14-PowerVFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Programmable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 21V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 1.87V
- Current - Output:
- 8A
- Frequency - Switching:
- 200kHz ~ 2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-QFN (3x4)
MP8867GLE-Z FAQ
1.How can I place an order for MP8867GLE-Z through Aetrix?
Please submit a Request for Quotation (RFQ) for MP8867GLE-Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MP8867GLE-Z reliable?
The price and inventory of MP8867GLE-Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MP8867GLE-Z is usually 5 days.
3.What payment methods are accepted for MP8867GLE-Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MP8867GLE-Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MP8867GLE-Z?
MP8867GLE-Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MP8867GLE-Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MP8867GLE-Z?
For technical support, including MP8867GLE-Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MP8867GLE-Z requirements.
6.How does Aetrix verify that MP8867GLE-Z is sourced from the original manufacturer or authorized distributors?
All MP8867GLE-Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MP8867GLE-Z meets industry standards.
7.What is the process for return or replacement of MP8867GLE-Z?
All MP8867GLE-Z units undergo pre-shipment inspection (PSI). If there is an issue with MP8867GLE-Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MP8867GLE-Z part is unused and in its original packaging.
Return procedure for MP8867GLE-Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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