NXP Semiconductors MPC8347CVRAGD

Overview

MPC8347CVRAGD from Freescale Semiconductor is a PowerQUICC™ II Pro integrated host processor featuring an embedded PowerPC e300 core operating up to 667 MHz, dual 10/100/1000 Mbps Ethernet controllers (TSEC), DDR SDRAM controller supporting 32-/64-bit interfaces at up to 333 MHz (TBGA) or 266 MHz (PBGA), PCI 2.2-compliant 32-bit/66 MHz interface, and hardware security engine with AES-128/192/256, DES/3DES, SHA-1/256, and RSA acceleration - deployed in network edge routers, industrial gateways, and secure communications appliances.

For engineers reviewing the MPC8347CVRAGD datasheet, MPC8347CVRAGD pinout, MPC8347CVRAGD application, or MPC8347CVRAGD equivalent, this page delivers verified technical context, package mapping (PBGA-672), validated pin functions, real-world use cases, and two confirmed alternative parts with documented functional and application-level differences.

Technical Context

The MPC8347CVRAGD implements a superscalar PowerPC e300 core with 32 KB instruction and 32 KB data L1 caches, lockable cache segments, and dynamic power management. Its DDR SDRAM controller supports programmable timing for DDR-1, four memory banks (up to 1 GB each), ECC, page mode (16 open pages), and registered DIMM compatibility with 2.5-V SSTL2 I/O.

It integrates dual IEEE 802.3-compliant TSECs with RGMII/GMII/TBI/RTBI/ MII physical layer support, 9.6-Kbyte jumbo frame handling, 2-Kbyte TX/RX FIFOs per channel, and MII management interface. The security engine contains four crypto-channels, PKEU (RSA/ECC), DEU (DES/3DES), AESU (AES-128/192/256), AFEU (RC4), MDEU (SHA-1/256, MD5), and RNG - all accessible via descriptor-based DMA.

Key Specifications

Pinout & Package

Package: PBGA-672 (Plastic Ball Grid Array, 27 mm × 27 mm, 1.0 mm pitch). Pinout validated per Freescale MPC8347E Hardware Specifications Rev. 11, Section 18.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar integrated host processor applications.

Compared with MPC8347CVRAGD, MPC8349CVRAGD offers higher DDR bandwidth in TBGA but sacrifices PBGA compatibility, while MPC8360CVRAGD delivers stronger crypto performance and higher core speed but removes USB host functionality and alters local bus behavior - making MPC8347CVRAGD the optimal balance for general-purpose secure networking with peripheral extensibility.

Availability

MPC8347CVRAGD is available at Aetrix Electronics and suitable for network edge routers, industrial protocol gateways, and secure wireless access points requiring stable component supply across extended product lifecycles.

Supply support for MPC8347CVRAGD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors since 2015) designed high-performance embedded processors for networking, automotive, and industrial markets before its acquisition.

The MPC8347CVRAGD belongs to the PowerQUICC™ II Pro family, engineered specifically for cost-sensitive, power-efficient integrated host processors in secure wired/wireless infrastructure equipment - emphasizing hardware-accelerated networking, memory subsystem reliability, and real-time determinism.

FAQ

What is the maximum DDR-1 data rate supported by the MPC8347CVRAGD?

The MPC8347CVRAGD supports DDR-1 data rates up to 266 MHz in the PBGA-672 package variant (as confirmed in Freescale MPC8347E Hardware Specifications Rev. 11, Section 6). This corresponds to a 533 MT/s transfer rate on a 64-bit bus. The TBGA-672 variant supports 333 MHz, but MPC8347CVRAGD is PBGA-packaged and therefore limited to 266 MHz. The DDR controller includes full ECC, programmable timing, and registered DIMM support - essential for robust packet buffering in networking applications using MPC8347CVRAGD.

Does the MPC8347CVRAGD include hardware encryption acceleration?

Yes, the MPC8347CVRAGD integrates a dedicated security engine with four crypto-channels supporting AES-128/192/256 (ECB/CBC/CTR/CCM), DES/3DES (ECB/CBC), SHA-1/256, MD5, HMAC, RSA-2048, elliptic curve cryptography, and RC4. These units operate independently via descriptor-based DMA, enabling full offload of IPSec, SSL/TLS, and IEEE 802.11i processing without CPU intervention - a core capability documented in Section 1 of the MPC8347E Hardware Specifications. This makes MPC8347CVRAGD suitable for secure gateway and firewall implementations.

What package type and pin count does the MPC8347CVRAGD use?

The MPC8347CVRAGD uses a PBGA-672 package: Plastic Ball Grid Array with 672 solder balls, 27 mm × 27 mm body size, and 1.0 mm ball pitch. This is explicitly confirmed in Freescale's ordering information (Section 23) and pin listing (Section 18) of the MPC8347E Hardware Specifications Rev. 11. The "RAGD" suffix in MPC8347CVRAGD denotes RoHS-compliant, lead-free, PBGA packaging - distinct from the TBGA variant used in higher-speed derivatives like MPC8349E. Pin functions are fully documented for this package in the specification.

Can the MPC8347CVRAGD operate as both a USB host and device?

Yes, the MPC8347CVRAGD includes a dual-role USB 2.0 controller compliant with USB Specification Rev. 2.0, supporting both host and device modes (USB On-The-Go). In host mode, it implements EHCI-compatible operation with one downstream-facing port; in device mode, it provides six programmable endpoints and one upstream-facing port. External PHY connectivity is supported via UTMI+, serial, or ULPI interfaces - as detailed in Sections 9 and 9.1 of the MPC8347E Hardware Specifications. This flexibility enables MPC8347CVRAGD-based designs to connect to USB peripherals or act as a USB device for firmware updates.

What is the function of the HRESET and SRESET pins on the MPC8347CVRAGD?

HRESET and SRESET are open-drain active-low reset outputs on the MPC8347CVRAGD. HRESET is asserted first during power-on initialization and remains active for at least 512 PCI_SYNC_IN cycles; SRESET follows, negated 16 cycles after HRESET negation. Both signals drive external logic to synchronize reset across attached peripherals (e.g., PHYs, DDR chips). Their timing relationships and electrical characteristics (VIH/VIL, leakage) are specified in Tables 8 and 9 of the MPC8347E Hardware Specifications. This two-stage reset sequence ensures deterministic initialization of the MPC8347CVRAGD and its subsystems.