NXP Semiconductors MPC8347ECVRAGD

Overview

MPC8347ECVRAGD from NXP Semiconductors (formerly Freescale) is a PowerQUICC™ II Pro integrated host processor featuring an embedded PowerPC e300 core operating up to 667 MHz, dual 10/100/1000-Mbps Ethernet controllers (TSECs), DDR SDRAM controller supporting 32-/64-bit interfaces at up to 333 MHz (TBGA), PCI 2.2 interface, and hardware security engine with AES-128/192/256, DES/3DES, SHA-1/256, and RSA acceleration. It targets network edge routers, industrial gateways, and secure embedded communications systems.

For engineers reviewing the MPC8347ECVRAGD datasheet, MPC8347ECVRAGD pinout, MPC8347ECVRAGD application, or MPC8347ECVRAGD equivalent, this page delivers verified technical context, validated package mapping (PBGA-620), confirmed pinout per Section 18 of the Rev. 11 Hardware Specifications, real-world application constraints for DDR timing and TSEC RGMII interfacing, and two field-deployed alternative processors with documented functional trade-offs.

Technical Context

The MPC8347ECVRAGD implements a superscalar PowerPC e300 core with 32-Kbyte instruction and 32-Kbyte data L1 caches, lockable cache segments, and dynamic power management. Its DDR SDRAM controller supports programmable timing for DDR-1, four memory banks (up to 1 Gbyte each), ECC, and registered DIMM compatibility with 2.5-V SSTL2 I/O.

It integrates dual IEEE 802.3-compliant TSECs with GMII/RGMII/TBI/RTBI physical layer support, 9.6-Kbyte jumbo frame handling, and RMON statistics; a PCI 2.2 host/agent interface with 32-bit/66-MHz operation and parity; and a dedicated security engine with four crypto-channels, PKEU (RSA up to 2048-bit), AESU (128/192/256-bit keys), and MDEU (SHA-1/256, MD5).

Key Specifications

Pinout & Package

The MPC8347ECVRAGD is packaged in a 620-pin PBGA (Plastic Ball Grid Array) with 27 × 27 mm body size, 1.0-mm ball pitch, and RoHS-compliant lead-free finish. Pin assignments follow the mechanical and electrical layout defined in Section 18 "Package and Pin Listings" of the MPC8347E Hardware Specifications Rev. 11.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar integrated host processor applications.

Compared with MPC8349ECVRAGD, the MPC8347ECVRAGD offers proven DDR-1 stability and lower power at 533 MHz, while MPC8548CZQMBG trades integrated crypto for PCIe bandwidth and SerDes flexibility-making MPC8347ECVRAGD optimal for cost-sensitive, crypto-heavy, DDR-1-based networking platforms.

Availability

MPC8347ECVRAGD is available at Aetrix Electronics and suitable for industrial gateways, enterprise branch routers, and secure wireless access points requiring stable component supply across extended product lifecycles.

Supply support for MPC8347ECVRAGD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep heritage in Power Architecture-based processors.

The MPC8347ECVRAGD belongs to the PowerQUICC™ II Pro family, designed specifically for cost-optimized, secure, and feature-rich embedded networking applications including edge routing, industrial gateways, and storage controllers.

FAQ

What is the maximum DDR data rate supported by the MPC8347ECVRAGD in PBGA packaging?

The MPC8347ECVRAGD supports DDR-1 SDRAM at up to 266 MHz data rate in the PBGA-620 package, delivering 4.2 GB/s peak bandwidth on the 64-bit interface. This is confirmed in Section 6 of the Hardware Specifications Rev. 11, which specifies 266 MHz for PBGA and 333 MHz only for TBGA variants. The MPC8347ECVRAGD's DDR controller includes programmable timing registers and full ECC support to maintain integrity at this rate.

Does the MPC8347ECVRAGD include hardware acceleration for TLS/SSL protocol processing?

Yes, the MPC8347ECVRAGD includes a dedicated security engine with AESU, MDEU, and ARC4 units that accelerate core TLS/SSL operations: AES-128/192/256 in CBC/CTR/CCM modes, SHA-1/256 for message digests, and HMAC for authentication. These units operate independently of the e300 core, enabling full SSL/TLS handshake offload as documented in Section 1.4 of the Hardware Specifications Rev. 11. The MPC8347ECVRAGD does not implement full protocol stack firmware but provides the cryptographic primitives required by OpenSSL or wolfSSL.

Can the MPC8347ECVRAGD operate in PCI agent mode with a stable 66 MHz PCI clock?

Yes, the MPC8347ECVRAGD supports PCI agent mode with a stable 66 MHz PCI clock applied to the PCI_SYNC_IN pin, as specified in Table 7 (CLKIN AC Timing) and Section 13 of the Hardware Specifications Rev. 11. In this configuration, the device uses the incoming PCI clock for synchronization while maintaining independent CSB and core PLL operation. The MPC8347ECVRAGD's PCI interface complies fully with PCI Specification Revision 2.2 and supports 32-bit/66-MHz transactions with parity and selectable coherency.

What are the power supply sequencing requirements for reliable startup of the MPC8347ECVRAGD?

The MPC8347ECVRAGD does not require strict power supply sequencing, but Freescale recommends applying VDD (core) before OVDD/GVDD/LVDD and asserting PORESET before supplies stabilize to minimize unintended I/O driving during ramp-up. This guidance appears in Section 2.2 "Power Sequencing" of the Hardware Specifications Rev. 11. All supplies-VDD, AVDD, GVDD, LVDD, and OVDD-must track within ±60 mV (VDD) or ±125–330 mV (I/O rails) and vary in the same direction to avoid latch-up. The MPC8347ECVRAGD's internal power-on reset circuitry ensures safe initialization when these conditions are met.

Is the MPC8347ECVRAGD pin-compatible with the MPC8347EA series?

No, the MPC8347ECVRAGD is not pin-compatible with the MPC8347EA series. The Hardware Specifications Rev. 11 explicitly states that revision 3.0 silicon (designated by part numbers ending in A or B) requires the separate MPC8347EA document due to changes in electrical characteristics and timing behavior. While both share the same PBGA-620 package footprint, differences in DDR timing margins, TSEC RGMII voltage thresholds, and PLL lock behavior necessitate board-level validation. The MPC8347ECVRAGD is qualified for revision 1.1 silicon and earlier, and direct substitution is not supported without redesign.