NXP Semiconductors MPC8347ECVRAGDB
- Part No.:
- MPC8347ECVRAGDB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 620-BBGA Exposed Pad
- Datasheet:
-
MPC8347ECVRAGDB.pdf
- Description:
- IC MPU MPC83XX 400MHZ 620HBGA
- Quantity:
- Payment:

- Shipping:

Inventory:3,503
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MPC8347ECVRAGDB from Freescale Semiconductor is a PowerQUICC™ II Pro integrated host processor featuring an embedded PowerPC e300 core operating up to 667 MHz, dual 10/100/1000 Mbps Ethernet controllers (TSECs), DDR SDRAM controller supporting 32-/64-bit interfaces at up to 333 MHz (TBGA), PCI 2.2-compliant 32-bit interface at 66 MHz, and hardware-accelerated security engine for IPSec/SSL/TLS. It targets network edge routers, industrial gateways, and secure embedded communications systems.
For engineers reviewing the MPC8347ECVRAGDB datasheet, MPC8347ECVRAGDB pinout, MPC8347ECVRAGDB application, or MPC8347ECVRAGDB equivalent, key selection criteria include e300 core frequency headroom, dual TSEC timing compliance with IEEE 802.3z/802.3ac, DDR-1 ECC support, PCI agent/host mode flexibility, and crypto-channel concurrency for IPSec throughput.
Technical Context
The MPC8347ECVRAGDB implements a superscalar PowerPC e300 core with 32-Kbyte instruction and 32-Kbyte data L1 caches, lockable cache regions, and dynamic power management. Its DDR SDRAM controller supports programmable timing, four banks (up to 1 Gbyte each), registered DIMM, and on-the-fly CKE-based self-refresh.
Dual TSECs provide full-duplex GMII/RGMII/TBI/RTBI and MII interfaces compliant with IEEE 802.3z, 802.3ac, and 802.3x, each with 2-Kbyte TX/RX FIFOs and RMON statistics. The security engine integrates four crypto-channels with dedicated PKEU (RSA/ECC), AESU (128/192/256-bit keys), DEU (DES/3DES), AFEU (RC4), and MDEU (SHA-1/SHA-256/MD5).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| e300 Core Frequency | Up to 667 MHz - enables high-throughput packet processing in routing/firewall applications |
| DDR Interface | 32-/64-bit DDR-1 at up to 333 MHz (TBGA) - supports 2.5-V SSTL2 I/O and full ECC for mission-critical memory integrity |
| TSEC Count & Speed | Dual 10/100/1000 Mbps controllers - provides independent LAN/WAN or redundant link capability with jumbo frame (9.6 KB) support |
| PCI Interface | 32-bit, 66 MHz, PCI 2.2-compliant - allows direct attachment of legacy peripherals or co-processors with parity and address translation |
| Security Engine | Four crypto-channels with PKEU/AESU/DEU/AFEU/MDEU - delivers concurrent IPSec/SSL offload without CPU intervention |
| USB Support | Dual-role USB 2.0 controller (EHCI-compatible) - enables host/device mode switching for firmware updates or peripheral bridging |
| Power Supply | VDD = 1.2 V ± 60 mV; GVDD = 2.5 V ± 125 mV; OVDD/LVDD = 3.3 V ± 330 mV - requires tightly tracked multi-rail sequencing |
Pinout & Package
The MPC8347ECVRAGDB is housed in a 672-pin TBGA (Thin Ball Grid Array) package with 1.0 mm ball pitch, designed for high-density PCB layouts in networking equipment. Thermal pad exposed on underside for enhanced heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN | Primary clock input | Accepts 66 MHz max external reference for system PLL; used in PCI host mode |
| PCI_SYNC_IN | PCI synchronization input | Provides clock reference in PCI agent mode; AC specs match PCI 3.3-V signaling |
| PORESET, HRESET, SRESET | Reset control signals | Asynchronous active-low reset hierarchy: PORESET initiates full power-on sequence; HRESET/SRESET drive external logic |
| MCK[0:3], MDQ[0:63], MDQS[0:8] | DDR memory interface | Source-synchronous 64-bit data + 9 strobes; supports 333 MHz operation with tDISKEW ≤ 750 ps (333 MHz) |
| TSEC0_TXD[0:3], TSEC0_RXD[0:3] | First TSEC MII interface | 4-bit nibble-wide MII PHY interface; supports 10/100 Mbps full/half-duplex per IEEE 802.3u |
| PCI_AD[0:31], PCI_CBE[0:3]#, PCI_PAR | PCI address/data bus | 32-bit multiplexed address/data lines with byte enable and parity; operates at 33/66 MHz |
Key Features
| Feature | Design Value |
|---|---|
| Lockable L1 cache segments | Enables deterministic real-time response by preventing critical code/data eviction during burst traffic |
| Programmable DDR timing registers | Allows fine-tuning of tRCD, tRP, tRAS for diverse DDR-1 chip vendors without hardware change |
| On-chip PCI-to-memory streaming | Eliminates CPU overhead for DMA transfers between PCI peripherals and DDR memory |
| Hardware CRC generation/checking | Offloads Ethernet frame CRC-32 computation from e300 core, reducing latency in line-rate forwarding |
| GPIO multiplexing with digital filtering | 52 pins shared across I²C, SPI, DUART, timers - on-chip spike rejection prevents false interrupts on noisy industrial buses |
Applications
| Industrial Secure Gateway | Enterprise Branch Router |
|---|---|
Use Scenario: Connecting OT networks (Modbus TCP, PROFINET) to IT infrastructure with TLS-encrypted telemetry and firewall rules. IC Role / Device Role / Timing Role: Central host processor executing Linux-based routing stack, managing dual TSECs as WAN/LAN interfaces, and accelerating IPsec SA setup via security engine. Use Value: Hardware crypto offload achieves 150+ Mbps ESP throughput while maintaining sub-50 µs interrupt latency for deterministic PLC communication. |
Use Scenario: Deploying compact branch office routers with VoIP, QoS, and stateful firewall in space-constrained enclosures. IC Role / Device Role / Timing Role: Integrated host processor running OpenWrt, using DDR controller for packet buffering, PCI for optional wireless module, and USB for console recovery. Use Value: Single-chip integration reduces BOM count by 12 components versus discrete MPU + PHY + crypto ASIC solutions. |
| Network Attached Storage Controller | Telecom Access Node |
Use Scenario: Embedded NAS appliance with iSCSI target, SMB/CIFS file sharing, and RAID 5 acceleration. IC Role / Device Role / Timing Role: Host processor managing SATA bridge via local bus, handling Ethernet packet I/O via TSECs, and performing SHA-256 hashing for SMB signing. Use Value: Dual TSECs enable link aggregation (802.3ad) for 2 Gbps NAS throughput; ECC DDR prevents silent corruption of stored metadata. |
Use Scenario: DSLAM or GPON OLT control plane handling SNMP, TR-069, and VLAN-aware bridging for 128+ subscribers. IC Role / Device Role / Timing Role: Control processor executing carrier-grade Linux, using GPIO for alarm monitoring, I²C for temperature sensors, and timers for precise SLA measurement. Use Value: Eight general-purpose timers support simultaneous 15-minute SLA polling cycles across multiple subscriber groups without software scheduling jitter. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated host processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8349EVRAGDB | Higher e300 core frequency (up to 800 MHz); identical pinout and peripheral set; supports DDR-2 (not DDR-1) | Better suited for compute-intensive firewall/NAT where >667 MHz headroom is required; DDR-2 support enables larger, faster memory subsystems | Select MPC8349EVRAGDB when upgrading performance-critical designs without changing PCB layout |
| MPC8377ERVAGDB | Adds PCIe 1.0 x1 interface and dual USB 2.0 host ports; removes one TSEC; same e300 core speed and DDR-1 support | Optimized for PCIe-based expansion (e.g., cellular modem, FPGA accelerator) rather than dual-Gigabit Ethernet redundancy | Choose MPC8377ERVAGDB for applications requiring PCIe connectivity over second Ethernet port |
Compared with MPC8347ECVRAGDB, MPC8349EVRAGDB offers higher clock headroom and DDR-2 readiness for future-proofing, while MPC8377ERVAGDB trades one TSEC for PCIe to enable heterogeneous compute expansion-neither is pin-compatible without validation of revised power delivery and signal integrity.
Availability
MPC8347ECVRAGDB is available at Aetrix Electronics and suitable for industrial gateways, enterprise branch routers, network-attached storage controllers, and telecom access nodes requiring stable component supply across extended product lifecycles.
Supply support for MPC8347ECVRAGDB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Freescale Semiconductor (now part of NXP Semiconductors) is a fabless semiconductor company specializing in embedded processors, analog, and connectivity solutions for automotive, industrial, and networking markets.
The MPC8347ECVRAGDB belongs to the PowerQUICC™ II Pro family, designed specifically for cost-sensitive, high-reliability networking and communications infrastructure requiring integrated processing, I/O, and security acceleration.
FAQ
What is the maximum DDR-1 data rate supported by the MPC8347ECVRAGDB?
The MPC8347ECVRAGDB supports DDR-1 SDRAM at up to 333 MHz in the TBGA package variant, delivering 5.3 GB/s peak bandwidth on the 64-bit interface. This rating is validated for revision 1.1 silicon and applies only to TBGA packages; PBGA variants are limited to 266 MHz. The controller includes programmable timing registers and full ECC support to ensure reliability at rated speeds.
Does the MPC8347ECVRAGDB support PCIe interface?
No, the MPC8347ECVRAGDB does not include a PCIe interface. It features a PCI 2.2-compliant 32-bit bus operating at up to 66 MHz. PCIe support was introduced in later PowerQUICC II Pro derivatives such as the MPC8377E. Designers requiring PCIe must select an alternative part or add a PCIe-to-PCI bridge IC.
How many crypto-channels does the security engine in the MPC8347ECVRAGDB provide?
The MPC8347ECVRAGDB security engine contains four independent crypto-channels, each capable of executing multi-command descriptor chains. These channels dynamically allocate execution units (PKEU, AESU, DEU, AFEU, MDEU) to process concurrent IPSec, SSL/TLS, or SRTP sessions without CPU intervention, enabling line-rate encryption for dual Gigabit Ethernet streams.
What is the function of the CFG_RESET_SOURCE pins on the MPC8347ECVRAGDB?
The CFG_RESET_SOURCE[0:2] pins on the MPC8347ECVRAGDB configure the primary reset source during power-on initialization, selecting between PORESET assertion, HRESET assertion, or SRESET assertion. These configuration signals must be sampled within 4 clock cycles after PORESET negation and determine the boot sequence flow, including clock source selection and PLL initialization parameters.
Is the MPC8347ECVRAGDB pin-compatible with the MPC8347EA series?
No, the MPC8347ECVRAGDB is not pin-compatible with the MPC8347EA series. The EA revision (introduced in silicon revision 3.0) includes electrical and timing changes documented separately in the MPC8347EA Hardware Specifications, particularly affecting DDR interface behavior and PLL lock times. Migration requires board-level validation and may need schematic modifications.
MPC8347ECVRAGDB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 620-BBGA Exposed Pad
- Series:
- MPC83xx
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- PowerPC e300
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 400MHz
- Co-Processors/DSP:
- Security; SEC
- RAM Controllers:
- DDR
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 + PHY (2)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Cryptography, Random Number Generator
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 620-HBGA (29x29)
- Additional Interfaces:
- DUART, I2C, PCI, SPI
MPC8347ECVRAGDB FAQ
1.How can I place an order for MPC8347ECVRAGDB through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8347ECVRAGDB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8347ECVRAGDB reliable?
The price and inventory of MPC8347ECVRAGDB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8347ECVRAGDB is usually 5 days.
3.What payment methods are accepted for MPC8347ECVRAGDB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8347ECVRAGDB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8347ECVRAGDB?
MPC8347ECVRAGDB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8347ECVRAGDB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8347ECVRAGDB?
For technical support, including MPC8347ECVRAGDB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8347ECVRAGDB requirements.
6.How does Aetrix verify that MPC8347ECVRAGDB is sourced from the original manufacturer or authorized distributors?
All MPC8347ECVRAGDB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8347ECVRAGDB meets industry standards.
7.What is the process for return or replacement of MPC8347ECVRAGDB?
All MPC8347ECVRAGDB units undergo pre-shipment inspection (PSI). If there is an issue with MPC8347ECVRAGDB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8347ECVRAGDB part is unused and in its original packaging.
Return procedure for MPC8347ECVRAGDB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MPC8347ECVRAGDB Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

