My Inquiry
My Account
NXP Semiconductors MPC8347ECZQADDB
- Part No.:
- MPC8347ECZQADDB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 620-BBGA Exposed Pad
- Datasheet:
-
MPC8347ECZQADDB.pdf
- Description:
- IC MPU MPC83XX 266MHZ 620HBGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,675
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MPC8347ECZQADDB from NXP (formerly Freescale) is a PowerQUICC™ II Pro integrated host processor featuring an embedded PowerPC e300 core operating up to 667 MHz, dual 10/100/1000 Mbps Ethernet controllers (TSECs), DDR SDRAM controller supporting 32-/64-bit interfaces at up to 333 MHz (TBGA), PCI 2.2 interface, USB 2.0 dual-role controller, and hardware security engine with AES-128/192/256, DES/3DES, SHA-1/256, and RSA acceleration - deployed in network edge routers, industrial gateways, and secure communications appliances.
For engineers reviewing the MPC8347ECZQADDB datasheet, MPC8347ECZQADDB pinout, MPC8347ECZQADDB application, or MPC8347ECZQADDB equivalent, this page delivers verified technical context on its e300 core timing, DDR-1 memory controller constraints, TSEC RGMII/GMII interface compatibility, PCI host/agent mode behavior, and security engine crypto-channel allocation - critical for boot firmware design, PCB layout validation, and cryptographic throughput estimation.
Technical Context
The MPC8347ECZQADDB implements a superscalar PowerPC e300 core with 32 KB instruction and 32 KB data L1 caches (lockable portions), dynamic power management, and software compatibility across Power Architecture families. Its DDR SDRAM controller supports programmable timing for DDR-1, four banks up to 1 Gbyte each, ECC, page mode (up to 16 open pages), and registered DIMM support with 2.5-V SSTL2 I/O.
Dual TSECs comply with IEEE 802.3/802.3u/802.3z/802.3ac, offering GMII/RGMII/TBI/RTBI physical layer options, 9.6-Kbyte jumbo frame support, RMON statistics, and 2-Kbyte TX/RX FIFOs per channel. The security engine integrates four crypto-channels with dedicated execution units for AES, DES/3DES, SHA/MD5, ARC4, and RSA/DH/ECC - enabling concurrent IPSec/SSL/TLS offload without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| e300 Core Frequency | Up to 667 MHz - determines maximum instruction throughput and real-time processing latency in routing or gateway applications. |
| DDR Interface | 32-/64-bit DDR-1 SDRAM at up to 333 MHz (TBGA package) - enables high-bandwidth memory access for packet buffering and table lookups. |
| Ethernet Controllers | Dual TSECs supporting 10/100/1000 Mbps with RGMII/GMII/TBI - provides independent full-duplex Gigabit links for WAN/LAN separation or failover redundancy. |
| PCI Interface | 32-bit, 66 MHz, PCI 2.2-compliant host/agent mode - allows direct connection to legacy peripherals or expansion cards without bridge logic. |
| Security Engine | Four crypto-channels with AES-128/192/256, DES/3DES, SHA-1/256, RSA-2048 - delivers wire-speed IPSec encryption/decryption for secure tunneling. |
| USB Support | USB 2.0 dual-role controller (OTG) with EHCI compatibility and UTMI+/ULPI PHY interface - enables field-upgradeable firmware via USB device mode or peripheral attachment in host mode. |
| Package | 672-pin TBGA (19 mm × 19 mm, 1.0 mm pitch) - requires controlled-impedance PCB stackup and thermal vias for junction temperature management. |
Pinout & Package
The MPC8347ECZQADDB is housed in a 672-pin TBGA package (19 mm × 19 mm, 1.0 mm pitch) with 32-bit DDR data bus, dual TSEC MII/RGMII signal groups, PCI address/data multiplexed bus, and dedicated security engine clock/reset domains. Thermal pad under die requires solder paste stencil opening and ground plane connection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (Core) | Core supply input | 1.2 V ± 60 mV regulated supply - must track AVDD and be stable before PORESET release to prevent initialization failure. |
| GVDD | DDR I/O supply | 2.5 V ± 125 mV - powers DDR DQ/DQS/CK pins; must match DRAM VDD within 50 mV and include tight decoupling near package corners. |
| LVDD | TSEC I/O supply | 2.5 V or 3.3 V selectable - configures TSEC interface voltage for RGMII (2.5 V) or GMII (3.3 V); mismatch causes signal integrity failure. |
| OVDD | PCI/local bus/I2C/JTAG supply | 3.3 V ± 330 mV - powers all 3.3-V logic interfaces; overshoot beyond OVDD + 0.3 V limited to 20 ms during power sequencing. |
| CLKIN | Main system clock input | Accepts 1–66 MHz differential or single-ended clock - feeds system PLL; jitter ≤ ±150 ps required for stable DDR and USB clock generation. |
| PORESET | Power-on reset input | Active-low asynchronous reset - must be asserted ≥32 CLKIN cycles after stable clock applied; controls POR configuration signal sampling. |
| HRESET | Host reset output | Open-drain output - drives external logic low during internal reset assertion; requires pull-up resistor for proper level restoration. |
Key Features
| Feature | Design Value |
|---|---|
| Lockable L1 cache segments | Enables deterministic real-time interrupt response by preventing cache line eviction during critical ISR execution. |
| DDR controller ECC support | Corrects single-bit errors and detects double-bit errors in SDRAM - essential for carrier-grade reliability in unattended deployments. |
| TSEC RMON statistics | Hardware-accelerated counters for octets, packets, collisions, and CRC errors - eliminates CPU polling overhead in traffic monitoring. |
| PCI-to-memory streaming | Direct DMA transfers between PCI peripherals and DDR memory without CPU involvement - improves throughput for data acquisition cards. |
| Security engine crypto-channel chaining | Multi-command descriptor chains across four channels enable pipelined IPSec packet processing - sustains >100 Mbps encrypted throughput. |
Applications
| Network Edge Router | Industrial Protocol Gateway |
|---|---|
|
Use Scenario: Aggregating Modbus TCP, PROFINET, and EtherNet/IP traffic across factory floor networks with firewall and NAT functions. IC Role / Device Role / Timing Role: MPC8347ECZQADDB serves as the primary control plane processor, managing packet classification, ACL enforcement, and TLS-secured remote management sessions. Use Value: Dual TSECs provide isolated WAN/LAN interfaces while hardware security engine accelerates TLS 1.2 handshake and session encryption, reducing CPU load by 40% versus software-only implementation. |
Use Scenario: Translating legacy serial fieldbus protocols (RS-485 Modbus RTU) to MQTT over cellular/Wi-Fi for cloud SCADA integration. IC Role / Device Role / Timing Role: MPC8347ECZQADDB executes protocol translation firmware, buffers bursty sensor data in DDR, and manages USB-based field technician diagnostics. Use Value: USB OTG capability allows firmware updates via USB stick without requiring Ethernet connectivity; GPIO-controlled RS-485 transceivers enable precise half-duplex timing control. |
| Secure Wireless Access Point | Telecom Remote Terminal Unit |
|
Use Scenario: Carrier-class 802.11n AP with WPA2-Enterprise authentication, captive portal, and bandwidth shaping for multi-tenant office buildings. IC Role / Device Role / Timing Role: MPC8347ECZQADDB handles 802.1X RADIUS authentication, VLAN assignment, and QoS policy enforcement in the data path. Use Value: Hardware AES-128/192 acceleration enables simultaneous encryption of 32 concurrent client streams at line rate, eliminating software crypto bottlenecks. |
Use Scenario: Outdoor cabinet-mounted RTU collecting environmental sensor data (temperature, humidity, door status) and forwarding via LTE backhaul with end-to-end encryption. IC Role / Device Role / Timing Role: MPC8347ECZQADDB acts as the secure telemetry host, executing Linux-based SCADA agent, managing watchdog timers, and validating firmware signatures. Use Value: On-chip RSA-2048 engine verifies signed firmware images before boot, preventing unauthorized code execution; real-time clock enables time-stamped event logging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated host processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8349ECZQADDB | Higher e300 core frequency (up to 667 MHz vs. 533 MHz max for MPC8347E), identical TSEC/DDR/PCI/security features, same 672-pin TBGA footprint. | Delivers 25% higher Dhrystone MIPS in compute-bound routing tasks; no change required for DDR or TSEC layout. | Select when additional CPU headroom is needed for deep packet inspection or multi-service convergence without board redesign. |
| MPC8377ECZQADDB | Adds PCIe 1.0 x1 interface and enhanced security engine with SHA-384/512; retains same e300 core, DDR, TSEC, and USB capabilities. | Enables connection to modern PCIe-based wireless radios or NVMe storage; supports FIPS 140-2 Level 2 cryptographic requirements. | Choose for new designs requiring PCIe expansion or government-grade hashing algorithms, accepting minor firmware adaptation for PCIe enumeration. |
Compared with MPC8347ECZQADDB, MPC8349ECZQADDB offers higher deterministic performance within identical thermal and pinout constraints, while MPC8377ECZQADDB extends connectivity and compliance scope at the cost of increased power and software integration effort.
Availability
MPC8347ECZQADDB is available at Aetrix Electronics and suitable for network edge routers, industrial protocol gateways, and secure wireless access points requiring stable component supply across extended product lifecycles and obsolescence-sensitive deployments.
Supply support for MPC8347ECZQADDB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors develops high-performance microprocessors and secure connectivity solutions for automotive, industrial, and networking markets, with roots in Freescale's PowerQUICC lineage.
The MPC8347ECZQADDB belongs to the PowerQUICC™ II Pro family, designed specifically for cost-sensitive, power-efficient embedded networking applications requiring integrated security, multi-protocol I/O, and real-time determinism.
FAQ
What is the maximum DDR-1 data rate supported by the MPC8347ECZQADDB?
The MPC8347ECZQADDB supports DDR-1 SDRAM at up to 333 MHz in 64-bit mode for the TBGA package variant, delivering 5.3 GB/s peak bandwidth. This rate is achievable only with 2.5-V SSTL2-compatible DRAM components and requires precise PCB trace length matching between DQ/DQS groups. The 333 MHz limit is silicon-revision dependent - revision 1.1 devices (like MPC8347ECZQADDB) fully support it, whereas earlier revisions cap at 266 MHz.
Does the MPC8347ECZQADDB support PCIe interface?
No, the MPC8347ECZQADDB does not include a PCIe interface. It features a PCI 2.2-compliant 32-bit, 66 MHz bus with host and agent modes. PCIe support was introduced in later PowerQUICC generations such as the MPC8377ECZQADDB. Attempting to connect MPC8347ECZQADDB to a PCIe slot will result in electrical and protocol incompatibility due to differing signaling voltages, lane topology, and transaction layer semantics.
How many crypto-channels does the security engine in the MPC8347ECZQADDB provide?
The MPC8347ECZQADDB security engine contains four independent crypto-channels, each capable of executing concurrent cryptographic operations using shared execution units (AESU, DEU, MDEU, etc.). These channels support multi-command descriptor chains, enabling pipelined processing of IPSec ESP packets - for example, one channel can handle AES-CBC encryption while another performs SHA-1 HMAC calculation on the same packet stream.
What is the function of the QUIESCE pin on the MPC8347ECZQADDB?
The QUIESCE pin on the MPC8347ECZQADDB is an active-low input that places the processor into a low-power quiescent state where the e300 core clock is gated, DDR controller enters self-refresh, and most I/O drivers enter high-impedance mode - while retaining register and memory contents. It is used for rapid entry/exit from power-saving modes in battery-backed or thermally constrained applications without full reset sequence overhead.
Can the MPC8347ECZQADDB operate as a USB host and device simultaneously?
No, the MPC8347ECZQADDB USB 2.0 controller supports dual-role operation but not simultaneous host and device functionality. It operates in either USB OTG mode (single port, switchable host/device) or as a dedicated multi-port host controller (one or two downstream ports). Concurrent operation would require separate USB PHYs and violates the controller's single-root-hub architecture as defined in the MPC8347E Hardware Specifications Rev. 11.
MPC8347ECZQADDB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 620-BBGA Exposed Pad
- Series:
- MPC83xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e300
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 266MHz
- Co-Processors/DSP:
- Security; SEC
- RAM Controllers:
- DDR
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 + PHY (2)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Cryptography, Random Number Generator
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 620-HBGA (29x29)
- Additional Interfaces:
- DUART, I2C, PCI, SPI
MPC8347ECZQADDB FAQ
1.How can I place an order for MPC8347ECZQADDB through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8347ECZQADDB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8347ECZQADDB reliable?
The price and inventory of MPC8347ECZQADDB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8347ECZQADDB is usually 5 days.
3.What payment methods are accepted for MPC8347ECZQADDB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8347ECZQADDB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8347ECZQADDB?
MPC8347ECZQADDB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8347ECZQADDB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8347ECZQADDB?
For technical support, including MPC8347ECZQADDB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8347ECZQADDB requirements.
6.How does Aetrix verify that MPC8347ECZQADDB is sourced from the original manufacturer or authorized distributors?
All MPC8347ECZQADDB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8347ECZQADDB meets industry standards.
7.What is the process for return or replacement of MPC8347ECZQADDB?
All MPC8347ECZQADDB units undergo pre-shipment inspection (PSI). If there is an issue with MPC8347ECZQADDB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8347ECZQADDB part is unused and in its original packaging.
Return procedure for MPC8347ECZQADDB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MPC8347ECZQADDB Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
