My Inquiry
My Account
NXP Semiconductors MPC8347ECZUAJDB
- Part No.:
- MPC8347ECZUAJDB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 672-LBGA
- Datasheet:
-
MPC8347ECZUAJDB.pdf
- Description:
- IC MPU MPC83XX 533MHZ 672LBGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,924
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MPC8347ECZUAJDB from Freescale Semiconductor is a PowerQUICC™ II Pro integrated host processor featuring an embedded PowerPC e300 core operating up to 667 MHz, dual 10/100/1000 Mbps Ethernet controllers (TSECs), DDR SDRAM controller supporting 32-/64-bit interfaces at up to 333 MHz (TBGA), PCI 2.2-compliant 32-bit/66 MHz interface, and hardware security engine with AES-128/192/256, DES/3DES, SHA-1/256, and RSA acceleration - deployed in network edge routers and industrial gateways requiring deterministic real-time packet processing.
For engineers reviewing the MPC8347ECZUAJDB datasheet, MPC8347ECZUAJDB pinout, MPC8347ECZUAJDB application, or MPC8347ECZUAJDB equivalent, key selection criteria include e300 core frequency headroom, TSEC RGMII/GMII timing compliance, DDR-1 ECC support, PCI agent/host mode flexibility, and hardware crypto-channel concurrency for IPSec/SSL offload in resource-constrained embedded systems.
Technical Context
The MPC8347ECZUAJDB implements a superscalar PowerPC e300 core with 32 KB instruction and 32 KB data L1 caches (lockable portions), dynamic power management, and software compatibility across Power Architecture-based Freescale families. Its DDR SDRAM controller supports programmable timing, four banks up to 1 Gbyte each, registered DIMM, and on-the-fly CKE-based self-refresh.
Two TSEC modules provide IEEE 802.3/802.3u/802.3z-compliant 10/100/1000 Mbps operation with RGMII/GMII/TBI interfaces, 9.6-Kbyte jumbo frame handling, and RMON statistics. The security engine integrates four crypto-channels with dedicated execution units for AES, DES/3DES, SHA/MD5, RSA, and RC4, enabling concurrent algorithm processing without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| e300 Core Frequency | Up to 667 MHz - enables high-throughput packet forwarding and control-plane processing in Layer 3 routing applications. |
| DDR Interface | 32-/64-bit DDR-1 SDRAM at up to 333 MHz (TBGA) - supports up to 4 GB total memory with ECC and page-mode optimization. |
| TSEC Throughput | Dual 10/100/1000 Mbps Ethernet controllers - delivers full-duplex line-rate performance per port with hardware-accelerated checksum and VLAN tagging. |
| PCI Interface | 32-bit, 66 MHz, PCI 2.2-compliant - provides low-latency peripheral expansion with host bridge and agent mode support. |
| Security Engine | Four crypto-channels with AES-128/192/256, DES/3DES, SHA-1/256, RSA-2048 - offloads IPSec/SSL/TLS processing to reduce CPU utilization by >70% in secure tunneling. |
| USB Support | Dual-role USB 2.0 controller (EHCI-compatible) - enables both host and device functionality with high-speed (480 Mbps) and full-speed (12 Mbps) modes. |
| Power Supply | VDD = 1.2 V ± 60 mV; GVDD = 2.5 V ± 125 mV; OVDD/LVDD = 3.3 V ± 330 mV - requires tightly tracked multi-rail sequencing for stable operation. |
Pinout & Package
The MPC8347ECZUAJDB is housed in a 676-pin TBGA (Thin Ball Grid Array) package with 1.0 mm ball pitch, designed for high-density PCB layouts and thermal dissipation in fanless networking equipment. Pin assignments follow Freescale's standardized PowerQUICC II Pro layout with dedicated banks for DDR, TSEC, PCI, and local bus signals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MDQ[0:63] | DDR Data Bus | 64-bit bidirectional data path supporting burst transfers and ECC parity generation/checking. |
| MCK[0:1] | DDR Clock | Differential clock pair driving DDR SDRAM; supports source-synchronous timing with tDISKEW < 750 ps at 333 MHz. |
| TSEC0_TXD[0:3] | Gigabit Ethernet Transmit | RGMII transmit data lines for first TSEC; requires matched trace length ≤ 500 mils for skew control. |
| TSEC1_RX_CTL | Gigabit Ethernet Receive Control | RGMII receive control signal for second TSEC; sampled synchronously with RX_CLK to recover MII/RGMII frames. |
| PCI_AD[0:31] | PCI Address/Data Multiplexed Bus | 32-bit multiplexed address/data lines compliant with PCI 2.2 timing; supports burst reads/writes and delayed transactions. |
| HRESET | Hardware Reset Output | Open-drain reset signal asserted during power-on or watchdog timeout; drives external peripherals and PHYs. |
| CLKIN | Main System Clock Input | Accepts 33–66 MHz single-ended clock; feeds system PLL to derive CSB, DDR, and TSEC clocks with ±150 ps jitter tolerance. |
Key Features
| Feature | Design Value |
|---|---|
| Lockable L1 Cache | Enables deterministic real-time interrupt response by preventing cache eviction of critical ISR code and data. |
| Programmable DDR Timing | Allows fine-tuning of tRCD, tRP, tRAS, and CAS latency to match specific DDR-1 SDRAM parts across temperature and voltage corners. |
| PCI-to-Memory Streaming | Eliminates CPU involvement in large DMA transfers between PCI peripherals and DDR memory, reducing latency by up to 40%. |
| On-Chip RNG | Provides cryptographically secure random numbers for IKE key exchange and TLS session initialization without external entropy sources. |
| GPIO Multiplexing | 52 pins shared across DUART, I²C, SPI, timers, and interrupt inputs - enables flexible board-level signal routing and debug interface assignment. |
Applications
| Network Edge Router | Industrial Protocol Gateway |
|---|---|
Use Scenario: Aggregating fieldbus traffic (Modbus TCP, EtherNet/IP) into IP backbone with firewall and QoS enforcement. IC Role / Device Role / Timing Role: MPC8347ECZUAJDB acts as the primary control-plane processor and data-path accelerator, managing TSEC packet steering, ACL lookups, and crypto offload for encrypted tunnels. Use Value: Hardware AES and SHA engines reduce CPU load during TLS 1.2 handshake by 85%, enabling sustained 200 Mbps encrypted throughput at < 15% core utilization. | Use Scenario: Bridging legacy RS-485 PLC networks to MQTT-based cloud SCADA via cellular/Wi-Fi uplink. IC Role / Device Role / Timing Role: MPC8347ECZUAJDB executes protocol translation firmware while using DUARTs for serial device interfacing and USB host mode for 3G/LTE modem attachment. Use Value: Dual TSECs enable simultaneous WAN (cellular router) and LAN (industrial Ethernet) connectivity with independent VLAN segmentation and rate limiting. |
| Secure Remote Terminal Unit (RTU) | Multi-Service Access Node |
Use Scenario: Deployed in unattended substations for encrypted telemetry collection, firmware OTA updates, and tamper-resistant logging. IC Role / Device Role / Timing Role: MPC8347ECZUAJDB serves as trusted execution environment with secure boot, hardware key storage, and runtime integrity monitoring via watchdog and timer subsystems. Use Value: On-chip RSA-2048 acceleration validates signed firmware images in < 120 ms, meeting IEC 62443-3-3 SL2 boot-time requirements. | Use Scenario: Providing DSL/cable broadband aggregation with VoIP, IPTV, and home automation services in residential gateways. IC Role / Device Role / Timing Role: MPC8347ECZUAJDB manages QoS scheduling across three TSEC ports, runs SIP stack on e300 core, and handles USB mass storage for media sharing. Use Value: Integrated PCI interface connects to ADSL2+ PHY without external bridge, reducing BOM cost by $1.80 and PCB area by 120 mm². |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated host processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8349ECZUAJDB | Higher e300 core frequency (up to 800 MHz); identical pinout and peripheral set; supports DDR2 (not DDR1). | Required for designs needing >667 MHz deterministic processing or DDR2 memory bandwidth; not drop-in for DDR1-only boards. | Select MPC8349ECZUAJDB when upgrading performance headroom or migrating to DDR2; verify DDR controller register mapping changes. |
| MPC8360ECZUAJDB | Adds dual PCI Express x1 lanes and enhanced security engine with SHA-384; same e300 core speed but larger die and higher power. | Suitable for next-gen carrier-grade CPE requiring PCIe-based wireless co-processors or FIPS 140-2 Level 3 compliance. | Choose MPC8360ECZUAJDB only if PCIe or extended crypto algorithms are mandatory; expect 25% higher thermal design power. |
Compared with MPC8349ECZUAJDB and MPC8360ECZUAJDB, the MPC8347ECZUAJDB offers optimal balance of proven DDR1 integration, TSEC feature set, and thermal efficiency for cost-sensitive industrial networking - avoiding unnecessary complexity or power overhead where DDR2 or PCIe are not required.
Availability
MPC8347ECZUAJDB is available at Aetrix Electronics and suitable for network edge routers, industrial protocol gateways, secure remote terminal units (RTUs), and multi-service access nodes requiring stable component supply across extended product lifecycles.
Supply support for MPC8347ECZUAJDB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Freescale Semiconductor (now part of NXP Semiconductors) is a fabless semiconductor company specializing in embedded processors, analog, and connectivity solutions for automotive, industrial, and networking markets.
The MPC8347ECZUAJDB belongs to the PowerQUICC™ II Pro family, designed specifically for cost-optimized, power-efficient integrated host processors in wired/wireless infrastructure equipment requiring real-time packet processing and hardware security acceleration.
FAQ
What is the maximum DDR-1 data rate supported by the MPC8347ECZUAJDB?
The MPC8347ECZUAJDB supports DDR-1 SDRAM at up to 333 MHz in the TBGA package variant, delivering 5.3 GB/s peak bandwidth on the 64-bit interface. This rate is validated for revision 1.1 silicon and earlier; later revisions (A/B suffix) require consultation of the MPC8347EA hardware specifications. The MPC8347ECZUAJDB DDR controller includes full ECC support, programmable timing registers, and registered DIMM compatibility - essential for reliable operation in telecom and industrial environments.
Does the MPC8347ECZUAJDB support PCI Express?
No, the MPC8347ECZUAJDB does not support PCI Express. It implements a legacy PCI 2.2-compliant 32-bit/66 MHz interface with host bridge and agent mode capabilities. For PCIe connectivity, designers must select the MPC8360ECZUAJDB or later PowerQUICC III derivatives. The MPC8347ECZUAJDB PCI interface provides robust peripheral expansion for Ethernet PHYs, flash controllers, and FPGA co-processors but lacks PCIe's point-to-point topology and higher bandwidth.
How many crypto algorithms does the MPC8347ECZUAJDB hardware security engine accelerate?
The MPC8347ECZUAJDB security engine accelerates five core algorithm families: AES (128/192/256-bit keys in ECB/CBC/CTR/CCM modes), DES/3DES (ECB/CBC), SHA-1/SHA-256, MD5, and RSA up to 2048 bits. It also includes RC4 stream cipher and a true random number generator (RNG). These functions execute concurrently across four crypto-channels, enabling full IPSec ESP/AH and SSL/TLS offload without CPU intervention - a capability confirmed in the MPC8347E Hardware Specifications Rev. 11, Section 1.4.
What is the function of the QUIESCE pin on the MPC8347ECZUAJDB?
The QUIESCE pin on the MPC8347ECZUAJDB is an active-low input that places the processor into a low-power quiescent state, halting all internal clocks except those needed for wake-up detection. When asserted, it disables the e300 core, DDR controller, and peripheral buses while preserving register contents and SRAM state. This pin enables rapid system suspend/resume cycles in battery-backed or energy-conscious applications. Its electrical characteristics match other reset inputs (VIH ≥ 2.0 V, VIL ≤ 0.8 V) and are specified in Table 8 of the MPC8347ECZUAJDB hardware reference.
Can the MPC8347ECZUAJDB operate as a USB host and device simultaneously?
No, the MPC8347ECZUAJDB USB controller supports dual-role operation but not simultaneous host and device mode. It can be configured either as a USB 2.0 device (with one upstream-facing port and six endpoints) or as a USB 2.0 host (with EHCI-compliant root hub and one downstream-facing port). The hardware lacks separate transceivers or OTG negotiation logic for concurrent roles. Designers requiring simultaneous USB host/device functionality must implement external USB switches or select alternative SoCs with dedicated OTG PHYs.
MPC8347ECZUAJDB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 672-LBGA
- Series:
- MPC83xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e300
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 533MHz
- Co-Processors/DSP:
- Security; SEC
- RAM Controllers:
- DDR
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 + PHY (2)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Cryptography, Random Number Generator
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 672-LBGA (35x35)
- Additional Interfaces:
- DUART, I2C, PCI, SPI
MPC8347ECZUAJDB FAQ
1.How can I place an order for MPC8347ECZUAJDB through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8347ECZUAJDB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8347ECZUAJDB reliable?
The price and inventory of MPC8347ECZUAJDB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8347ECZUAJDB is usually 5 days.
3.What payment methods are accepted for MPC8347ECZUAJDB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8347ECZUAJDB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8347ECZUAJDB?
MPC8347ECZUAJDB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8347ECZUAJDB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8347ECZUAJDB?
For technical support, including MPC8347ECZUAJDB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8347ECZUAJDB requirements.
6.How does Aetrix verify that MPC8347ECZUAJDB is sourced from the original manufacturer or authorized distributors?
All MPC8347ECZUAJDB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8347ECZUAJDB meets industry standards.
7.What is the process for return or replacement of MPC8347ECZUAJDB?
All MPC8347ECZUAJDB units undergo pre-shipment inspection (PSI). If there is an issue with MPC8347ECZUAJDB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8347ECZUAJDB part is unused and in its original packaging.
Return procedure for MPC8347ECZUAJDB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MPC8347ECZUAJDB Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
