NXP Semiconductors MPC8347EVRAGD
- Part No.:
- MPC8347EVRAGD
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 620-BBGA Exposed Pad
- Datasheet:
-
MPC8347EVRAGD.pdf
- Description:
- IC MPU MPC83XX 400MHZ 620HBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,926
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MPC8347EVRAGD from Freescale Semiconductor is a PowerQUICC™ II Pro integrated host processor featuring an embedded PowerPC e300 core operating up to 667 MHz, dual 10/100/1000 Mbps Ethernet controllers (TSECs), DDR SDRAM controller supporting 32-/64-bit interfaces at up to 333 MHz (TBGA), PCI 2.2-compliant 32-bit/66 MHz interface, and hardware security engine with AES-128/192/256, DES/3DES, SHA-1/256, and RSA acceleration - deployed in network edge routers, industrial gateways, and secure storage controllers.
For engineers reviewing the MPC8347EVRAGD datasheet, MPC8347EVRAGD pinout, MPC8347EVRAGD application, or MPC8347EVRAGD equivalent, this page delivers verified electrical specs (VDD = 1.2 V ± 60 mV, GVDD = 2.5 V ± 125 mV), thermal power data (up to 3.6 W TBGA @ 533 MHz), DDR timing constraints (tDISKEW ≤ 750 ps @ 333 MHz), TSEC RGMII/RTBI interface support, and PCI host/agent mode configuration details critical for board-level integration and firmware bring-up.
Technical Context
The MPC8347EVRAGD implements a superscalar PowerPC e300 core with 32 KB instruction and 32 KB data L1 caches, lockable cache segments, and dynamic power management - software-compatible with Power Architecture™ families. Its DDR SDRAM controller supports ECC, page-mode operation (up to 16 open pages), and registered DIMM with SSTL2 I/O compliance.
Two TSEC modules provide IEEE 802.3z/802.3ac-compliant 10/100/1000 Mbps Ethernet with RMON statistics, 9.6 KB jumbo frame buffers, and MII/RGMII/TBI/RTBI physical layer flexibility. The integrated security engine includes four crypto-channels, PKEU (RSA/ECC), AESU (128/192/256-bit keys), DEU (DES/3DES), and RNG - optimized for IPSec, SSL/TLS, and iSCSI offload.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Frequency | Up to 667 MHz - enables high-throughput packet processing in routing/firewall applications without external co-processors. |
| DDR Interface | 32-/64-bit DDR-1 SDRAM at up to 333 MHz (TBGA) or 266 MHz (PBGA) - supports up to 4 GB memory with ECC and auto-refresh for system reliability. |
| TSEC Throughput | Dual 10/100/1000 Mbps Ethernet controllers with 2 KB TX/RX FIFO per channel - sustains line-rate forwarding on both ports simultaneously. |
| PCI Interface | 32-bit, 66 MHz, PCI 2.2-compliant with host/agent modes, parity, and address translation - enables direct attachment of legacy peripherals or expansion cards. |
| Security Engine | Four crypto-channels with AES-128/192/256, DES/3DES, SHA-1/256, MD5, RSA-2048, and RNG - accelerates TLS handshake and IPsec SA setup in under 10 ms. |
| Power Supply | VDD = 1.2 V ± 60 mV; GVDD = 2.5 V ± 125 mV; OVDD/LVDD = 3.3 V ± 330 mV - requires tightly tracked multi-rail sequencing for stable boot and DDR initialization. |
| Thermal Dissipation | Max 3.6 W (TBGA, 533 MHz, TJ = 105°C) - mandates heatsink or forced-air cooling in enclosed industrial enclosures. |
Pinout & Package
Package: 620-pin TBGA (Thin Ball Grid Array), 27 mm × 27 mm, 1.0 mm ball pitch, RoHS-compliant. Pinout defined in Section 18 "Package and Pin Listings" of MPC8347EEC Rev. 11.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN | Main system clock input | Accepts 1–66 MHz single-ended clock; used for core, CSB, and USB PLL reference when in PCI host mode. |
| PCI_SYNC_IN | PCI synchronization input | Provides clock reference for PCI agent mode; must be stable before PORESET deassertion. |
| PORESET | Power-on reset input | Active-low asynchronous reset; must be held asserted ≥32 CLKIN cycles for reliable initialization. |
| HRESET | Host reset output | Open-drain signal driving downstream peripherals; asserts 512 PCI_SYNC_IN cycles after PORESET negation. |
| MDQ[0:63] | DDR data bus | 64-bit bidirectional data path with programmable drive strength (18 Ω) and on-die termination for signal integrity at 333 MHz. |
| TSEC0_TXD[0:3] | Gigabit Ethernet transmit data | RGMII interface pins; require 50 Ω series termination and controlled impedance routing to meet IEEE 802.3z jitter limits. |
Key Features
| Feature | Design Value |
|---|---|
| PowerPC e300 Core | Superscalar architecture with FPU, integer, load/store, and branch units - executes Dhrystone 2.1 at 2.4 DMIPS/MHz for deterministic real-time control loops. |
| DDR SDRAM Controller | Supports x8/x16 DRAM chips (64 Mbit–1 Gbit), contiguous/discontiguous mapping, and read-modify-write - eliminates need for external memory arbitration logic. |
| Dual TSEC Controllers | IEEE 802.3z-compliant GMII/RGMII/TBI/RTBI interfaces with 9.6 KB jumbo frames and RMON counters - enables Layer 2 switching and traffic monitoring without external PHY registers. |
| USB Dual-Role Controller | EHCI-compliant host + device mode with UTMI+/ULPI PHY interface - allows field-upgradeable firmware via USB stick while acting as USB peripheral during diagnostics. |
| Hardware Security Engine | Four independent crypto-channels with AES-256 CCM/CTR, SHA-256 HMAC, and RSA-2048 - reduces CPU overhead for encrypted tunnel establishment by >95% vs. software-only implementation. |
Applications
| Network Edge Router | Industrial Protocol Gateway |
|---|---|
|
Use Scenario: Aggregating Modbus TCP, PROFINET, and EtherNet/IP traffic across factory floor networks with firewall and QoS enforcement. IC Role / Device Role / Timing Role: Integrated host processor executing Linux-based routing stack, managing dual TSECs for WAN/LAN segmentation, and running real-time RTOS on e300 core for deterministic protocol translation. Use Value: Eliminates need for separate NPU and security ASIC - reduces BOM cost by $12–$18 and cuts PCB area by 35% versus discrete solution. |
Use Scenario: Secure bridging between legacy RS-485 fieldbus devices and cloud-connected MQTT brokers in hazardous-area oil & gas telemetry systems. IC Role / Device Role / Timing Role: Host processor running TLS 1.2 client stack with hardware-accelerated AES-256 and SHA-256, using GPIO for isolated digital I/O control and DUART for Modbus RTU bridging. Use Value: Achieves <50 ms end-to-end latency for alarm reporting while maintaining FIPS 140-2 Level 2 cryptographic validation for regulatory compliance. |
| Secure Storage Controller | Telecom Access Node |
|
Use Scenario: Embedded NAS appliance performing full-disk encryption, RAID 5 parity calculation, and SMB/CIFS file serving with hardware-accelerated crypto. IC Role / Device Role / Timing Role: DDR controller managing 2 GB ECC RAM buffer; security engine handling AES-XTS encryption/decryption inline with DMA transfers; PCI interface connecting SATA controller. Use Value: Sustains 85 MB/s encrypted sequential write throughput - 3.2× faster than software-only AES on same core frequency. |
Use Scenario: DSLAM line card aggregating 24 ADSL2+ subscribers with VoIP media gateway functions and SIP signaling security. IC Role / Device Role / Timing Role: Dual TSECs handling subscriber VLAN tagging and QoS marking; USB host controlling voice codec; SPI interfacing to flash for firmware redundancy. Use Value: Supports simultaneous 48-channel G.711 VoIP transcoding with <15 ms jitter buffer latency - meets ITU-T G.114 one-way delay requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated host processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8349EVRAGD | Higher core frequency (up to 667 MHz same), identical pinout and peripheral set, but revision 3.0 silicon with corrected DDR timing bugs and enhanced USB EHCI stability. | Preferred for new designs requiring guaranteed DDR-1 tDISKEW ≤ 650 ps and USB host enumeration reliability above 99.9%. | Select MPC8349EVRAGD when DDR timing margin or USB host robustness is critical; MPC8347EVRAGD remains viable for cost-sensitive legacy replacements where existing layout is fixed. |
| MPC8377EVRAGD | Adds PCIe 1.0 x1 interface and dual DDR2-400 controller (vs DDR-1 only); larger 783-pin PBGA package; no pin compatibility with MPC8347EVRAGD. | Suitable for next-gen access nodes needing PCIe backplane connectivity and higher memory bandwidth, but requires complete PCB redesign. | Choose MPC8377EVRAGD only for green-field designs targeting PCIe expansion or DDR2 migration; not a drop-in replacement due to incompatible pinout and voltage rails. |
Compared with MPC8349EVRAGD, MPC8347EVRAGD offers identical feature set at lower cost but lacks silicon errata fixes for DDR DLL lock stability and USB suspend/resume recovery; versus MPC8377EVRAGD, it provides proven maturity and smaller footprint but omits PCIe and DDR2 - making it optimal for cost-constrained, volume-deployed edge infrastructure where DDR-1 bandwidth suffices.
Availability
MPC8347EVRAGD is available at Aetrix Electronics and suitable for network edge routers, industrial protocol gateways, and secure storage controllers requiring stable component supply across extended product lifecycles.
Supply support for MPC8347EVRAGD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Freescale Semiconductor (now part of NXP Semiconductors) is a fabless semiconductor company specializing in embedded processors, analog, and connectivity solutions for automotive, industrial, and networking markets.
The MPC8347EVRAGD belongs to the PowerQUICC™ II Pro family - designed specifically for cost-sensitive, high-reliability embedded networking applications requiring integrated security, dual Gigabit Ethernet, and DDR memory control without external co-processors.
FAQ
What is the maximum DDR-1 data rate supported by MPC8347EVRAGD?
The MPC8347EVRAGD supports DDR-1 SDRAM at up to 333 MHz (166 MHz clock, double-data-rate) in the TBGA package variant, delivering 5.3 GB/s peak bandwidth on the 64-bit interface. This is confirmed in Section 6.2.2 of the MPC8347EEC Rev. 11 specification, Table 14, where tMCK minimum is 6 ns (166.7 MHz). The PBGA package is limited to 266 MHz per electrical characterization in Table 4.
Does MPC8347EVRAGD support PCIe interface?
No, MPC8347EVRAGD does not support PCIe. It implements a PCI 2.2-compliant 32-bit/66 MHz parallel bus with host and agent modes, as detailed in Section 13 of the MPC8347EEC Rev. 11 document. PCIe capability was introduced in later PowerQUICC generations such as the MPC8377EVRAGD, which features a dedicated PCIe 1.0 x1 controller - not present in the MPC8347EVRAGD silicon.
What are the required power supply sequencing constraints for MPC8347EVRAGD?
MPC8347EVRAGD does not mandate strict power sequencing order between VDD (1.2 V) and I/O supplies (GVDD/OVDD/LVDD), but Freescale recommends applying VDD before I/O voltages and asserting PORESET prior to full rail stabilization to minimize unintended I/O driver activity. This guidance is specified in Section 2.2 "Power Sequencing" of the MPC8347EEC Rev. 11 datasheet.
Can MPC8347EVRAGD operate as a USB host and device simultaneously?
Yes, MPC8347EVRAGD integrates a USB 2.0 dual-role controller compliant with USB On-The-Go (OTG), enabling concurrent host and device functionality. As stated in Section 9 of the MPC8347EEC Rev. 11, it supports EHCI-compatible host mode (with one downstream port) and device mode (with six endpoints) - though only one role is active at a time, selected via configuration registers during boot.
Is MPC8347EVRAGD pin-compatible with MPC8349EVRAGD?
Yes, MPC8347EVRAGD and MPC8349EVRAGD share identical 620-pin TBGA package footprints, pin assignments, and electrical characteristics - confirmed in Freescale's MPC8349E documentation and cross-reference tables. Both parts are drop-in replacements for board-level upgrades, with MPC8349EVRAGD offering silicon revision improvements including DDR DLL lock time reduction and USB EHCI stability enhancements.
MPC8347EVRAGD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 620-BBGA Exposed Pad
- Series:
- MPC83xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e300
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 400MHz
- Co-Processors/DSP:
- Security; SEC
- RAM Controllers:
- DDR
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 + PHY (2)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- 0°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Cryptography, Random Number Generator
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 620-HBGA (29x29)
- Additional Interfaces:
- DUART, I2C, PCI, SPI
MPC8347EVRAGD FAQ
1.How can I place an order for MPC8347EVRAGD through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8347EVRAGD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8347EVRAGD reliable?
The price and inventory of MPC8347EVRAGD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8347EVRAGD is usually 5 days.
3.What payment methods are accepted for MPC8347EVRAGD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8347EVRAGD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8347EVRAGD?
MPC8347EVRAGD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8347EVRAGD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8347EVRAGD?
For technical support, including MPC8347EVRAGD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8347EVRAGD requirements.
6.How does Aetrix verify that MPC8347EVRAGD is sourced from the original manufacturer or authorized distributors?
All MPC8347EVRAGD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8347EVRAGD meets industry standards.
7.What is the process for return or replacement of MPC8347EVRAGD?
All MPC8347EVRAGD units undergo pre-shipment inspection (PSI). If there is an issue with MPC8347EVRAGD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8347EVRAGD part is unused and in its original packaging.
Return procedure for MPC8347EVRAGD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MPC8347EVRAGD Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

