NXP Semiconductors MPC8347EVVAJDB
- Part No.:
- MPC8347EVVAJDB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 672-LBGA Exposed Pad
- Datasheet:
-
MPC8347EVVAJDB.pdf
- Description:
- IC MPU MPC83XX 533MHZ 672TBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,010
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Product details
Overview
MPC8347EVVAJDB from NXP (formerly Freescale) is a PowerQUICC II Pro integrated host processor built on Power Architecture® e300 core, operating up to 667 MHz with 32-Kbyte instruction and 32-Kbyte data L1 cache. It integrates dual 10/100/1000-Mbps Ethernet controllers (TSEC), DDR1/DDR2 SDRAM controller (up to 400 MHz in TBGA), PCI 2.3 interface, USB 2.0 dual-role controller, security engine with AES/DES/RSA acceleration, and I²C/DMA/DUART peripherals - deployed in network edge routers, industrial gateways, and secure communications appliances.
For engineers reviewing the MPC8347EVVAJDB datasheet, MPC8347EVVAJDB pinout, MPC8347EVVAJDB application, or MPC8347EVVAJDB equivalent, key selection criteria include e300 core frequency headroom, TSEC RGMII/GMII timing compliance, DDR2 1.8-V I/O voltage tolerance, PCI 3.3-V agent/host mode flexibility, and hardware-accelerated IPSec/SSL offload capability for real-time encrypted traffic handling.
Technical Context
The MPC8347EVVAJDB implements a superscalar e300 core with floating-point, integer, load/store, and branch units, coupled with dynamic power management and software compatibility across Power Architecture families. Its memory subsystem supports DDR1 (2.5-V SSTL2) and DDR2 (1.8-V SSTL2) with ECC, up to 4 banks × 1 Gbyte, and programmable timing for 266–400 MHz data rates depending on package.
Networking is handled by two IEEE 802.3-compliant TSECs with MII/RGMII/GMII/TBI interfaces, 9.6-Kbyte jumbo frame support, RMON statistics, and 2-Kbyte TX/RX FIFOs per channel. The security engine features four crypto-channels with dedicated AESU (128/192/256-bit keys), DEU (DES/3DES), PKEU (RSA up to 2048-bit), and MDEU (SHA-1/224/256, MD5).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| e300 Core Frequency | Up to 667 MHz - enables Dhrystone 2.1 DMIPS/MHz performance for real-time packet processing and control-plane tasks. |
| DDR/DDR2 Controller | 32-/64-bit interface, 266 MHz (PBGA) / 400 MHz (TBGA) max data rate - supports registered DIMMs and auto-refresh for embedded systems requiring persistent memory bandwidth. |
| TSEC Ethernet | Dual 10/100/1000-Mbps controllers with RGMII/GMII/TBI - delivers full-duplex gigabit throughput per port with hardware timestamping and jumbo frame support. |
| PCI Interface | 32-bit, 66 MHz, PCI 2.3-compliant - operates in host or agent mode with parity, prefetching, and five-master arbitration for peripheral expansion. |
| Security Engine | Four crypto-channels with AES-256, 3DES, RSA-2048, SHA-256 - accelerates IPSec/SSL/TLS at line rate without CPU overhead. |
| USB 2.0 | Dual-role (OTG) controller with EHCI-compatible host mode and device mode - supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation via external ULPI PHY. |
| Supply Voltages | VDD = 1.3 V ±60 mV (667 MHz), GVDD = 1.8 V ±90 mV (DDR2) or 2.5 V ±125 mV (DDR1), OVDD = 3.3 V ±330 mV - requires strict voltage tracking between VDD, AVDD, GVDD, LVDD, OVDD. |
Pinout & Package
Package: 672-pin TBGA (Thin Ball Grid Array), 35 mm × 35 mm, 1.0 mm ball pitch, RoHS-compliant. Thermal pad on underside for heatsink attachment; designed for industrial temperature range (–40°C to +105°C junction).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN | Primary clock input | Accepts 1–66 MHz single-ended reference clock; used in PCI host mode to drive system PLL and generate CSB, DDR, USB, and security clocks. |
| PCI_SYNC_IN | PCI synchronization input | Provides clock reference in PCI agent mode; determines tPCI_SYNC_IN timing for reset and configuration signal sampling. |
| HRESET, SRESET | Reset outputs | HRESET asserts hardware reset to external peripherals; SRESET signals soft reset to local bus devices; both are open-drain with 8 mA sink capability. |
| PORESET | Power-on reset input | Active-low asynchronous reset triggered during power ramp; must be held asserted ≥32 tCLKIN cycles before clock stabilization. |
| EC_GTX_CLK125 | Gigabit Ethernet reference clock output | 125 MHz differential clock for TSEC GMII/RGMII PHY interface; ±150 ps jitter; duty cycle 45–55% for GMII, 47–53% for RGMII. |
| DDR_DQ[0:63] | DDR/DDR2 data bus | 64-bit bidirectional data lines with programmable drive strength (18 Ω for DDR2); require on-die termination and matched trace lengths. |
Key Features
| Feature | Design Value |
|---|---|
| Lockable L1 cache portion | Enables deterministic real-time execution by preventing critical code/data from being evicted during interrupt-heavy operation. |
| Hardware ECC for DDR/DDR2 | Corrects single-bit errors and detects double-bit errors in SDRAM transactions - essential for carrier-grade reliability in unattended deployments. |
| PCI-to-memory streaming | Eliminates CPU involvement in large-block transfers between PCI peripherals and system memory - reduces latency and frees core cycles. |
| Programmable interrupt groups | Four priority-programmable interrupt groups with unique vector numbers - simplifies RTOS integration and ISR dispatch in multi-interrupt environments. |
| ULPI PHY interface | Reduces USB 2.0 pin count to 12 signals (vs. 32+ for UTMI) - lowers PCB layer count and routing complexity in space-constrained designs. |
Applications
| Network Edge Router | Industrial Protocol Gateway |
|---|---|
Use Scenario: Aggregating fieldbus traffic (Modbus TCP, PROFINET) into IP backbone with firewall and QoS enforcement. IC Role / Device Role / Timing Role: Central host processor executing Linux-based routing stack, managing dual TSECs for WAN/LAN segmentation, and running crypto-engine for IPsec tunnel encryption. Use Value: Hardware-accelerated AES-256 and SHA-256 enable 100+ Mbps encrypted throughput without degrading routing performance or increasing thermal load. |
Use Scenario: Bridging legacy RS-485/RS-232 field devices to MQTT/OPC UA cloud platforms in factory automation. IC Role / Device Role / Timing Role: Real-time protocol translation engine using DUARTs and GPIOs for serial interface control, local bus for flash/NOR boot, and DDR2 for firmware staging. Use Value: Lockable L1 cache and eight general-purpose timers ensure deterministic response to Modbus RTU polling cycles under variable network load. |
| Secure Wireless Access Point | Medical Imaging Data Concentrator |
Use Scenario: 802.11n AP with WPA3-Enterprise authentication, captive portal, and VLAN segregation for hospital Wi-Fi networks. IC Role / Device Role / Timing Role: Dual-TSEC handles wired uplink and wireless backhaul; security engine performs TLS handshake offload and certificate validation. Use Value: Four crypto-channels process concurrent SSL sessions for 50+ clients while maintaining <10 ms latency for VoIP and telemetry streams. |
Use Scenario: DICOM gateway aggregating ultrasound, X-ray, and MRI DICOM streams before compression and PACS upload. IC Role / Device Role / Timing Role: High-bandwidth DDR2 controller buffers raw image frames; USB 2.0 host connects to external storage; local bus manages FPGA co-processor for JPEG2000 encoding. Use Value: 400 MHz DDR2 interface sustains >600 MB/s sustained read/write for lossless medical image transfer without frame drop. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated host processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8349EVVAJDB | Same e300 core, higher DDR2 max speed (533 MHz), added SATA 1.0 controller, identical pinout and power envelope. | Better suited for storage-centric edge nodes requiring local disk caching or RAID-1 mirroring. | Select when SATA interface and higher DDR bandwidth are required; software migration is minimal due to architectural compatibility. |
| MPC8548CVMALG | e500v2 core (higher IPC), 1333 MT/s DDR2, PCIe x4, no integrated TSEC - requires external PHY and switch. | Targeted at high-throughput control plane in telecom infrastructure where PCIe expansion and deterministic latency outweigh integrated Ethernet convenience. | Choose for new designs needing PCIe scalability and higher single-thread performance; not drop-in due to different pinout and missing TSEC PHY logic. |
Compared with MPC8349EVVAJDB, the MPC8347EVVAJDB trades SATA and marginal DDR speed for lower BOM cost and proven qualification in long-lifecycle industrial deployments; versus MPC8548CVMALG, it offers integrated networking at the expense of PCIe flexibility and newer core architecture.
Availability
MPC8347EVVAJDB is available at Aetrix Electronics and suitable for network edge routers, industrial protocol gateways, secure wireless access points, and medical imaging data concentrators requiring stable component supply across extended product lifecycles.
Supply support for MPC8347EVVAJDB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors (formerly Freescale) is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in Power Architecture® and edge processing.
The MPC8347EVVAJDB belongs to the PowerQUICC II Pro family, designed specifically for cost-sensitive, power-efficient embedded networking and communications equipment requiring integrated security, dual gigabit Ethernet, and DDR memory control without external bridge chips.
FAQ
What is the maximum DDR2 data rate supported by the MPC8347EVVAJDB?
The MPC8347EVVAJDB supports DDR2 SDRAM at up to 400 MHz data rate in the TBGA package variant, corresponding to 800 MT/s. This is achieved with 1.8-V SSTL2 I/O, programmable timing, and hardware ECC - verified in revision 3.x silicon and later. The PBGA variant is limited to 266 MHz (533 MT/s). Actual achievable rate depends on board layout, DRAM part selection, and thermal conditions.
Does the MPC8347EVVAJDB support PCIe or only PCI?
The MPC8347EVVAJDB implements PCI Specification Revision 2.3 (32-bit, 66 MHz), not PCIe. It supports both PCI host bridge and agent modes, with features including parity, prefetching, and five-master arbitration. PCIe is absent - designs requiring PCIe must use later families like MPC85xx. The MPC8347EVVAJDB's PCI interface remains fully compatible with legacy add-in cards and bridge chips.
How many crypto algorithms does the MPC8347EVVAJDB security engine accelerate?
The MPC8347EVVAJDB security engine accelerates AES (128/192/256-bit keys in ECB/CBC/CTR/CCM), DES/3DES (ECB/CBC), RSA/DH up to 2048-bit, ECC (F2m/Fp up to 511-bit), SHA-1/224/256, MD5, HMAC, RC4, and random number generation. All are executed in dedicated hardware units across four independent crypto-channels - enabling concurrent IPSec, SSL, and iSCSI session offload without CPU intervention.
Is the MPC8347EVVAJDB pin-compatible with the MPC8347EA?
Yes, MPC8347EVVAJDB is a qualified, enhanced-speed grade of the MPC8347EA with identical 672-pin TBGA footprint, pin assignment, and electrical signaling. The 'V' suffix denotes extended temperature range (–40°C to +105°C), and 'JDB' indicates lead-free, RoHS-compliant packaging. Firmware and hardware designs for MPC8347EA are directly reusable with MPC8347EVVAJDB.
What USB modes does the MPC8347EVVAJDB support, and what PHY interface is required?
The MPC8347EVVAJDB supports USB 2.0 On-The-Go (dual-role) operation - functioning as either host or device. It requires an external PHY connected via ULPI (UTMI+ Low Pin Interface), which uses only 12 signals (vs. 32+ for full UTMI), reducing PCB complexity. The controller implements EHCI for high-speed host mode and standard device-mode endpoints - no internal PHY is integrated.
MPC8347EVVAJDB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 672-LBGA Exposed Pad
- Series:
- MPC83xx
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e300
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 533MHz
- Co-Processors/DSP:
- Security; SEC
- RAM Controllers:
- DDR
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 + PHY (2)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- 0°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Cryptography, Random Number Generator
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 672-TBGA (35x35)
- Additional Interfaces:
- DUART, I2C, PCI, SPI
MPC8347EVVAJDB FAQ
1.How can I place an order for MPC8347EVVAJDB through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8347EVVAJDB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8347EVVAJDB reliable?
The price and inventory of MPC8347EVVAJDB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8347EVVAJDB is usually 5 days.
3.What payment methods are accepted for MPC8347EVVAJDB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8347EVVAJDB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8347EVVAJDB?
MPC8347EVVAJDB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8347EVVAJDB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8347EVVAJDB?
For technical support, including MPC8347EVVAJDB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8347EVVAJDB requirements.
6.How does Aetrix verify that MPC8347EVVAJDB is sourced from the original manufacturer or authorized distributors?
All MPC8347EVVAJDB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8347EVVAJDB meets industry standards.
7.What is the process for return or replacement of MPC8347EVVAJDB?
All MPC8347EVVAJDB units undergo pre-shipment inspection (PSI). If there is an issue with MPC8347EVVAJDB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8347EVVAJDB part is unused and in its original packaging.
Return procedure for MPC8347EVVAJDB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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