NXP Semiconductors MPC8347VVAGDB

Overview

MPC8347VVAGDB from Freescale Semiconductor is a PowerQUICC™ II Pro integrated host processor featuring an embedded PowerPC e300 core operating up to 667 MHz, dual 10/100/1000 Mbps Ethernet controllers (TSECs), DDR SDRAM controller supporting 32-/64-bit interfaces at up to 333 MHz (TBGA), PCI 2.2-compliant 32-bit interface at 66 MHz, and hardware security engine with AES-128/192/256, DES/3DES, SHA-1/256, and RSA acceleration - deployed in network edge routers, industrial gateways, and secure communications appliances.

For engineers reviewing the MPC8347VVAGDB datasheet, MPC8347VVAGDB pinout, MPC8347VVAGDB application, or MPC8347VVAGDB equivalent, this page delivers verified silicon revision 1.1 specifications, TBGA-783 package mapping, DDR/PCI/Ethernet timing constraints, security engine crypto-channel architecture, and validated alternative processors for migration paths in legacy PowerQUICC-based designs.

Technical Context

The MPC8347VVAGDB implements a superscalar e300 core with 32 KB instruction and 32 KB data L1 caches (lockable portions), dynamic power management, and software compatibility across Power Architecture™ families. Its DDR controller supports programmable timing for DDR-1 SDRAM, ECC, page mode (up to 16 open pages), and registered DIMM with 2.5-V SSTL2 I/O.

Two TSEC modules comply with IEEE 802.3/802.3u/802.3z standards, offering GMII/RGMII/TBI/RTBI physical interfaces, 9.6-Kbyte jumbo frames, RMON statistics, and 2-Kbyte TX/RX FIFOs per channel. The security engine integrates four crypto-channels with dedicated execution units for AES, DES/3DES, SHA/MD5, RSA, and RC4, plus RNG and HMAC support.

Key Specifications

Pinout & Package

TBGA-783 package with 27 mm × 27 mm body, 1.0 mm ball pitch, and standard JEDEC MO-251 footprint. Thermal pad on underside requires solder paste stencil design per Freescale AN3703.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar integrated host processor applications.

Compared with MPC8347VVAGDB, MPC8349EVVAJDB offers higher compute density and DDR2 readiness for future-proofing, while MPC8377VRAGDB trades TSECs for SerDes/PCIe - making the former ideal for performance upgrades and the latter for serial infrastructure evolution.

Availability

MPC8347VVAGDB is available at Aetrix Electronics and suitable for network edge routers, industrial protocol gateways, and secure wireless access points requiring stable component supply across extended product lifecycles.

Supply support for MPC8347VVAGDB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors) is a fabless semiconductor company specializing in embedded processing, connectivity, and analog solutions for automotive, industrial, and networking markets.

The MPC8347VVAGDB belongs to the PowerQUICC™ II Pro family, designed specifically for cost-sensitive, high-reliability networking and communications equipment requiring integrated processing, security, and multi-protocol I/O in a single chip.

FAQ

What is the maximum DDR data rate supported by the MPC8347VVAGDB?

The MPC8347VVAGDB supports DDR-1 SDRAM at up to 333 MHz in TBGA packages, delivering 5.3 GB/s peak bandwidth on the 64-bit interface. This specification applies only to revision 1.1 silicon; later revisions (e.g., MPC8347EA) support DDR2 but require different timing and voltage settings. The MPC8347VVAGDB's DDR controller includes programmable timing registers, ECC generation/checking, and auto-refresh - all confirmed in Freescale document MPC8347EEC Rev. 11.

Does the MPC8347VVAGDB include hardware encryption acceleration?

Yes, the MPC8347VVAGDB integrates a dedicated security engine with four crypto-channels and execution units for AES-128/192/256, DES/3DES, SHA-1/256, MD5, RSA (up to 2048-bit), and RC4. It supports ECB/CBC/CTR/CCM modes and HMAC, enabling full IPSec/SSL/TLS offload. This capability is documented in Section 1.1 of the MPC8347EEC Rev. 11 specification and verified in Freescale application note AN3642.

What package type and pin count does the MPC8347VVAGDB use?

The MPC8347VVAGDB uses a TBGA-783 package: 27 mm × 27 mm body size, 1.0 mm ball pitch, JEDEC MO-251 compliant footprint. Pin functions include 64 DDR data lines, 4 DDR clocks, dual TSEC interfaces, PCI bus signals, and dedicated security engine control lines - all mapped in Section 18 of MPC8347EEC Rev. 11.

Can the MPC8347VVAGDB operate in PCI host mode?

Yes, the MPC8347VVAGDB supports PCI host bridge functionality per PCI Specification Revision 2.2, including memory prefetching, delayed read transactions, and address translation between host and peripheral spaces. It operates as a 32-bit, 66 MHz PCI master with five-master arbitration - confirmed in Section 13 of MPC8347EEC Rev. 11 and validated in Freescale reference design RD8347.

What is the recommended power sequencing for the MPC8347VVAGDB?

Freescale specifies that core voltage (VDD = 1.2 V) should be applied before I/O supplies (GVDD, LVDD, OVDD) and PORESET asserted prior to full rail stabilization. This sequence minimizes active driving on I/O pins during ramp-up. The MPC8347VVAGDB does not require strict voltage tracking order, but all rails must vary in the same direction - details are in Section 2.2 of MPC8347EEC Rev. 11.