NXP Semiconductors MPC8347ZQADDB

Overview

MPC8347ZQADDB from Freescale Semiconductor is a PowerQUICC™ II Pro integrated host processor featuring an embedded PowerPC e300 core operating up to 667 MHz, dual 10/100/1000 Mbps Ethernet controllers (TSECs), DDR SDRAM controller supporting 32-/64-bit interfaces at up to 333 MHz (TBGA), PCI 2.2-compliant 32-bit/66 MHz interface, and hardware security engine with AES-128/192/256, DES/3DES, SHA-1/256, and RSA acceleration - deployed in carrier-grade edge routers and industrial gateways requiring deterministic real-time packet processing.

For engineers reviewing the MPC8347ZQADDB datasheet, MPC8347ZQADDB pinout, MPC8347ZQADDB application, or MPC8347ZQADDB equivalent, this page delivers verified silicon revision–specific electrical specs (Rev. 1.1), DDR timing constraints (tDISKEW ≤ 750 ps @ 333 MHz), power sequencing guidance (VDD before OVDD), thermal limits (TJ = 105°C max), and validated alternative migration paths for legacy PowerQUICC II Pro designs.

Technical Context

The MPC8347ZQADDB implements a superscalar e300 core with 32 KB instruction and 32 KB data L1 caches, lockable cache segments, and dynamic power management - software-compatible with Power Architecture™ families. Its DDR controller supports registered DIMMs, ECC, auto-refresh, and CKE-based sleep mode, with timing validated for 2.5-V SSTL2 I/O.

Two TSEC modules provide IEEE 802.3z-compliant GMII/RGMII/TBI interfaces, 9.6-Kbyte jumbo frames, RMON statistics, and 2-Kbyte TX/RX FIFOs per channel. The security engine integrates four crypto-channels with dedicated AESU, DEU, PKEU, MDEU, and RNG units - enabling concurrent IPSec/SSL/TLS offload without CPU intervention.

Key Specifications

Pinout & Package

The MPC8347ZQADDB is housed in a 620-pin TBGA (Thin Ball Grid Array) package with 1.0 mm ball pitch, designed for high-density routing and thermal dissipation in networking equipment. Pin assignments follow Freescale's documented ball map for Rev. 1.1 silicon.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar integrated host processor applications.

Compared with MPC8347ZQADDB, MPC8349ZQADDB extends DDR bandwidth and USB flexibility, while MPC8377ZQADDB strengthens cryptographic primitives - both retain pin compatibility and software ABI alignment, enabling drop-in replacement where silicon revision and qualification allow.

Availability

MPC8347ZQADDB is available at Aetrix Electronics and suitable for carrier-grade edge routers, industrial protocol gateways, secure wireless backhaul units, and network attached storage controllers requiring stable component supply across extended product lifecycles.

Supply support for MPC8347ZQADDB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors) is a fabless semiconductor company specializing in embedded processors, analog, and connectivity solutions for automotive, industrial, and networking markets.

The MPC8347ZQADDB belongs to the PowerQUICC™ II Pro family - engineered for high-performance, low-latency packet processing in telecom infrastructure and mission-critical industrial systems with integrated security and memory subsystems.

FAQ

What is the maximum DDR data rate supported by the MPC8347ZQADDB?

The MPC8347ZQADDB supports DDR-1 SDRAM at up to 333 MHz in TBGA packages, delivering 5.3 GB/s peak bandwidth on the 64-bit interface. This is validated for Rev. 1.1 silicon per Freescale's MPC8347EEC Rev. 11 specification. Operation above 266 MHz requires registered DIMM support and strict adherence to tDISKEW ≤ 750 ps timing constraints. The MPC8347ZQADDB does not support DDR2 or LPDDR.

Does the MPC8347ZQADDB include hardware encryption acceleration?

Yes, the MPC8347ZQADDB integrates a dedicated security engine with four crypto-channels supporting AES-128/192/256 (ECB/CBC/CTR/CCM), DES/3DES (ECB/CBC), SHA-1/256, MD5, HMAC, RSA-2048, and elliptic curve cryptography. This enables full IPSec/SSL/TLS offload without CPU intervention - confirmed in Section 1.1 of the MPC8347EEC Rev. 11 datasheet.

What are the power sequencing requirements for the MPC8347ZQADDB?

Freescale specifies that VDD (1.2 V) must be applied before OVDD/LVDD/GVDD (3.3 V/2.5 V) during power ramp-up to minimize actively driven I/O states. PORESET must be asserted before supplies stabilize. All supplies - VDD, AVDD, GVDD, LVDD, OVDD - must track within ±60 mV/±125 mV/±330 mV tolerances and vary monotonically in the same direction, as defined in Table 2 of MPC8347EEC Rev. 11.

Is the MPC8347ZQADDB pin-compatible with other PowerQUICC II Pro processors?

The MPC8347ZQADDB shares the 620-ball TBGA package and pinout with MPC8349ZQADDB and MPC8377ZQADDB, enabling mechanical and layout compatibility. However, functional differences exist - e.g., MPC8349ZQADDB adds USB OTG support, and MPC8377ZQADDB enhances crypto algorithms. Software and timing validation remain required per application, as stated in Freescale's ordering information section.

What Ethernet standards does the MPC8347ZQADDB TSEC support?

The MPC8347ZQADDB dual TSEC modules comply with IEEE 802.3, 802.3u, 802.3x, 802.3z, and 802.3ac standards. They support 10/100 Mbps MII and 1000 Mbps GMII/RGMII/TBI/RTBI interfaces with full-duplex operation, jumbo frames up to 9.6 KB, RMON statistics, and hardware CRC generation/checking - all detailed in Section 8 of the MPC8347EEC Rev. 11 specification.