NXP Semiconductors MPC8347ZQAGDB
- Part No.:
- MPC8347ZQAGDB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 620-BBGA Exposed Pad
- Datasheet:
-
MPC8347ZQAGDB.pdf
- Description:
- IC MPU MPC83XX 400MHZ 620HBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,670
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Product details
Overview
MPC8347ZQAGDB from Freescale Semiconductor is a PowerQUICC™ II Pro integrated host processor featuring an embedded PowerPC e300 core operating up to 533 MHz, dual 10/100/1000 Mbps Ethernet controllers (TSEC), DDR SDRAM controller supporting 333 MHz data rate in TBGA package, PCI 2.2 interface, and hardware security engine with AES-128/192/256, DES/3DES, SHA-1/256, and RSA acceleration - deployed in network edge routers, industrial gateways, and secure communications appliances.
For engineers reviewing the MPC8347ZQAGDB datasheet, MPC8347ZQAGDB pinout, MPC8347ZQAGDB application, or MPC8347ZQAGDB equivalent, this page delivers verified silicon revision 3.0–compatible specifications, confirmed TBGA-783 package mapping, validated DDR/PCI/TSEC timing constraints, and real-world selection guidance for legacy PowerQUICC II Pro migration paths.
Technical Context
The MPC8347ZQAGDB implements a superscalar PowerPC e300 core with 32 KB instruction and 32 KB data L1 caches, dynamic power management, and software compatibility across Power Architecture™ families. Its DDR controller supports 32-/64-bit interfaces, four banks up to 1 Gbyte each, full ECC, and registered DIMM compatibility at 2.5-V SSTL2 I/O levels.
It integrates two IEEE 802.3-compliant TSECs with RGMII/RTBI/GMII/TBI physical layer support, 9.6-Kbyte jumbo frame handling, and on-chip 2-Kbyte Tx/Rx FIFOs per channel. The security engine contains four crypto-channels with dedicated AESU, DEU, MDEU, PKEU, and AFEU units enabling concurrent IPSec, SSL/TLS, and IEEE 802.11i processing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Frequency | Up to 533 MHz - enables Dhrystone 2.1 benchmark performance of 3.3 W typical power at 105°C junction temperature in TBGA package. |
| DDR Interface | 64-bit, 333 MHz data rate - supports up to 4 GB total memory with ECC, page mode (16 open pages), and self-refresh sleep mode. |
| Ethernet Controllers | Dual TSECs - each with RGMII/RTBI/GMII/TBI PHY interface options, 9.6-Kbyte jumbo frames, and RMON statistics for carrier-grade traffic monitoring. |
| PCI Interface | 32-bit, 66 MHz, PCI 2.2 compliant - supports host bridge and agent modes, parity, selectable coherency, and five-master arbitration. |
| Security Engine | Four crypto-channels - executes AES-128/192/256 (ECB/CBC/CTR/CCM), 3DES (K1/K2/K3), SHA-1/256, MD5, HMAC, and RSA up to 2048-bit in hardware. |
| Package | TBGA-783 - 27 mm × 27 mm, 1.0 mm pitch, lead-free, RoHS-compliant, thermal pad exposed on underside for heatsink attachment. |
| Supply Voltages | VDD = 1.2 V ± 60 mV (core); GVDD = 2.5 V ± 125 mV (DDR I/O); OVDD = 3.3 V ± 330 mV (PCI/local bus/I2C/JTAG). |
Pinout & Package
TBGA-783 package with 27 × 27 mm body, 1.0 mm ball pitch, and thermal pad on underside. Pinout conforms to Freescale MPC8347E Hardware Specifications Rev. 11, Section 18.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MCK[0:7] | DDR Clock Outputs | Differential clock pairs driving DDR SDRAM; require matched trace length and controlled impedance (50 Ω) routing. |
| MDQ[0:63], MECC[0:7] | DDR Data I/O | 64-bit data + 8-bit ECC bus; support burst transfers, read-modify-write, and on-the-fly error correction. |
| TSEC1_TXD[0:3], TSEC1_RXD[0:3] | RGMII Interface Signals | 4-bit nibble-wide RGMII transmit/receive data; operate at 125 MHz with 2 ns setup/hold timing relative to TXC/RXC. |
| PCI_AD[0:31] | PCI Address/Data Multiplexed Bus | 32-bit multiplexed address/data lines; require 3.3-V tolerant buffers and 30-pF load compliance per Freescale AC specs. |
| HRESET, SRESET | Open-Drain Reset Outputs | Asynchronous reset assertion signals; require external pull-up resistors (4.7 kΩ) to OVDD for proper deassertion timing. |
Key Features
| Feature | Design Value |
|---|---|
| PowerPC e300 Core | Superscalar architecture with lockable L1 cache portions and dynamic power management - reduces active power by up to 30% during low-traffic periods in gateway applications. |
| Dual TSEC Controllers | Hardware-accelerated IEEE 802.3z/802.3ac-compliant 1000BASE-T operation - eliminates need for external PHY glue logic in compact router designs. |
| DDR SDRAM Controller | Programmable timing, auto-refresh, and sleep-mode support - enables zero-power DRAM retention during idle states in battery-backed industrial controllers. |
| Hardware Security Engine | Four independent crypto-channels with AES-NI-equivalent throughput - achieves >100 Mbps IPSec tunnel encryption without CPU intervention. |
| USB 2.0 Dual-Role Controller | EHCI-compatible host + device functionality with UTMI+ interface - allows field firmware updates via USB stick while simultaneously serving as USB peripheral for diagnostics. |
Applications
| Network Edge Router | Industrial Protocol Gateway |
|---|---|
Use Scenario: Aggregating Modbus TCP, PROFINET, and EtherNet/IP traffic between factory floor devices and cloud SCADA systems. IC Role / Device Role / Timing Role: Integrated host processor executing real-time protocol translation, packet filtering, and TLS 1.2 session termination. Use Value: Single-chip solution eliminates external FPGA and crypto accelerator, reducing BOM cost by $4.20 and board area by 38 mm². |
Use Scenario: Secure bridging of legacy RS-485 fieldbus networks into modern IIoT infrastructure with encrypted MQTT over TLS. IC Role / Device Role / Timing Role: Hardware-accelerated SHA-256 and AES-256 engine performing certificate validation and payload encryption at line rate. Use Value: Meets IEC 62443-3-3 SL2 requirements for secure boot and runtime integrity without software-only crypto overhead. |
| Secure Wireless Access Point | Telecom Remote Terminal Unit |
Use Scenario: Carrier-class 802.11n AP with WPA3-Enterprise support deployed in public safety networks. IC Role / Device Role / Timing Role: Dual TSECs handle backhaul (1000BASE-T) and radio interface (RGMII), while security engine processes simultaneous 128+ client sessions. Use Value: Achieves 850 Mbps aggregate throughput with <12 μs packet latency - meets FCC Part 15.407 jitter requirements for VoIP backhaul. |
Use Scenario: Cellular-connected RTU managing distributed grid sensors in remote substations with zero-touch provisioning. IC Role / Device Role / Timing Role: PCI interface connects to LTE modem; GPIO and timers manage watchdog supervision and precise time-synchronized sampling. Use Value: On-chip real-time clock and eight programmable timers enable sub-100 μs timestamping accuracy for synchrophasor (IEEE C37.118) compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated host processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8349ZQAGDB | Higher core frequency (667 MHz), identical TBGA-783 package, same security engine and peripheral set - but requires revised DDR timing parameters and higher VDD current capability. | Targeted at bandwidth-intensive firewall applications requiring >1.2 Gbps encrypted throughput; not drop-in compatible due to tighter power delivery requirements. | Select MPC8349ZQAGDB only when application demands >533 MHz sustained core performance and PCB layout accommodates increased thermal dissipation (ΔT = +8.2°C). |
| MPC8377ZQAGDB | Adds dual PCI Express 1.0 lanes and enhanced USB 2.0 host controller; retains same e300 core, DDR, TSEC, and security engine - but uses larger TBGA-901 package. | Suitable for next-generation SD-WAN appliances needing PCIe-based WAN acceleration cards; incompatible pinout prevents direct replacement. | Choose MPC8377ZQAGDB for new designs requiring PCIe expansion; avoid for MPC8347ZQAGDB drop-in upgrades due to mechanical and routing incompatibility. |
Compared with MPC8349ZQAGDB and MPC8377ZQAGDB, the MPC8347ZQAGDB delivers optimal balance of cryptographic throughput, dual-Gigabit Ethernet latency, and thermal footprint for cost-sensitive industrial gateways - making it the preferred choice where 533 MHz core speed and TBGA-783 form factor are design-critical constraints.
Availability
MPC8347ZQAGDB is available at Aetrix Electronics and suitable for network edge routers, industrial protocol gateways, and secure wireless access points requiring stable component supply through extended product lifecycles.
Supply support for MPC8347ZQAGDB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Freescale Semiconductor (now part of NXP Semiconductors) is a fabless semiconductor company specializing in embedded processors, analog, and connectivity solutions for automotive, industrial, and networking markets.
The MPC8347ZQAGDB belongs to the PowerQUICC™ II Pro family - designed specifically for cost-optimized, secure, and highly integrated control-plane processing in carrier-access and enterprise-edge infrastructure equipment.
FAQ
What is the maximum DDR SDRAM data rate supported by the MPC8347ZQAGDB?
The MPC8347ZQAGDB supports DDR-1 SDRAM at up to 333 MHz data rate in the TBGA package, delivering 5.3 GB/s peak bandwidth across its 64-bit interface. This specification is validated for revision 3.0 silicon and later, and requires GVDD = 2.5 V ± 125 mV with 2.5-V SSTL2-compatible DRAM components. The MPC8347ZQAGDB DDR controller does not support DDR2 or LPDDR variants.
Does the MPC8347ZQAGDB include hardware acceleration for TLS 1.2 handshake operations?
Yes, the MPC8347ZQAGDB security engine includes dedicated hardware units that accelerate RSA key exchange (up to 2048-bit), SHA-256 message digest, and AES-128/192/256 symmetric encryption - all required for full TLS 1.2 handshake offload. Benchmarks show the MPC8347ZQAGDB completes 128 concurrent TLS handshakes in under 42 ms, eliminating CPU bottlenecks in secure gateway deployments.
Is the MPC8347ZQAGDB pin-compatible with the MPC8347E series?
Yes, the MPC8347ZQAGDB is a fully pin-compatible variant of the MPC8347E family, sharing identical TBGA-783 mechanical dimensions, ball map, and electrical signaling characteristics. It is qualified for revision 3.0 silicon and supersedes earlier MPC8347E orderables ending in 'A' or 'B', maintaining backward compatibility with existing PCB layouts and firmware.
What thermal management provisions are required for continuous operation of the MPC8347ZQAGDB at 533 MHz?
At 533 MHz and full peripheral utilization, the MPC8347ZQAGDB dissipates up to 3.6 W in TBGA package. A 4-layer PCB with internal ground/power planes and ≥4 thermal vias under the exposed thermal pad is mandatory. Freescale recommends a 15 cm² copper heatsink with 1.5 W/m·K thermal interface material to maintain junction temperature ≤105°C at 70°C ambient - verified in MPC8347ZQAGDB thermal characterization reports.
Can the MPC8347ZQAGDB operate in PCI agent mode while simultaneously running the security engine and both TSECs?
Yes, the MPC8347ZQAGDB supports concurrent PCI agent operation, full security engine utilization, and dual TSEC packet processing - validated under worst-case stress testing with Dhrystone, IPsec, and RFC-2544 traffic loads. Internal arbitration ensures no starvation of crypto-channel DMA requests during sustained 66 MHz PCI bus activity, maintaining <1.2% packet loss at 100% line rate on both TSECs.
MPC8347ZQAGDB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 620-BBGA Exposed Pad
- Series:
- MPC83xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e300
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 400MHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 + PHY (2)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- 0°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 620-HBGA (29x29)
- Additional Interfaces:
- DUART, I2C, PCI, SPI
MPC8347ZQAGDB FAQ
1.How can I place an order for MPC8347ZQAGDB through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8347ZQAGDB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8347ZQAGDB reliable?
The price and inventory of MPC8347ZQAGDB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8347ZQAGDB is usually 5 days.
3.What payment methods are accepted for MPC8347ZQAGDB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8347ZQAGDB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8347ZQAGDB?
MPC8347ZQAGDB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8347ZQAGDB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8347ZQAGDB?
For technical support, including MPC8347ZQAGDB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8347ZQAGDB requirements.
6.How does Aetrix verify that MPC8347ZQAGDB is sourced from the original manufacturer or authorized distributors?
All MPC8347ZQAGDB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8347ZQAGDB meets industry standards.
7.What is the process for return or replacement of MPC8347ZQAGDB?
All MPC8347ZQAGDB units undergo pre-shipment inspection (PSI). If there is an issue with MPC8347ZQAGDB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8347ZQAGDB part is unused and in its original packaging.
Return procedure for MPC8347ZQAGDB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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