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NXP Semiconductors MPC8347ZUAJDB
- Part No.:
- MPC8347ZUAJDB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 672-LBGA
- Datasheet:
-
MPC8347ZUAJDB.pdf
- Description:
- IC MPU MPC83XX 533MHZ 672LBGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,255
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Product details
Overview
MPC8347ZUAJDB from NXP (formerly Freescale) is a PowerQUICC™ II Pro integrated host processor featuring an embedded PowerPC e300 core operating up to 667 MHz, dual 10/100/1000-Mbps Ethernet controllers (TSECs), DDR SDRAM controller supporting 32-/64-bit interfaces at up to 333 MHz (TBGA), PCI 2.2-compliant 32-bit/66-MHz interface, and hardware-accelerated security engine for IPSec/SSL/TLS. It targets network edge routers, industrial gateways, and secure embedded communications systems.
For engineers reviewing the MPC8347ZUAJDB datasheet, MPC8347ZUAJDB pinout, MPC8347ZUAJDB application, or MPC8347ZUAJDB equivalent, key selection criteria include its e300 core frequency headroom, dual TSEC timing compliance with IEEE 802.3z/ac, DDR-1 ECC support, PCI agent/host mode flexibility, and integrated crypto-channel architecture with AES-256, SHA-256, and RSA-2048 acceleration.
Technical Context
The MPC8347ZUAJDB implements a superscalar PowerPC e300 core with 32-KB instruction and 32-KB data L1 caches (lockable portion), dynamic power management, and software compatibility across Power Architecture families. Its DDR SDRAM controller supports programmable timing, four banks up to 1 Gbyte each, registered DIMM, and on-the-fly CKE-based self-refresh.
Two independent TSEC modules provide full-duplex 1000BASE-X GMII/RGMII/TBI operation and MII for 10/100 Mbps, with 9.6-KB jumbo frame support, RMON statistics, and 2-KB Tx/Rx FIFOs per channel. The security engine integrates four crypto-channels with dedicated execution units for AES, DES/3DES, SHA/MD5, ARC4, and RSA/DH/ECC-enabling concurrent IPsec and SSL offload without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| e300 Core Frequency | Up to 667 MHz - enables real-time packet processing and multi-threaded control plane tasks in resource-constrained edge nodes. |
| DDR Interface | 32-/64-bit DDR-1 at 333 MHz (TBGA) - delivers up to 5.3 GB/s memory bandwidth for high-throughput forwarding tables and buffer management. |
| TSEC Count & Speed | Dual 10/100/1000-Mbps controllers - supports simultaneous WAN/LAN segmentation or redundant link failover in managed switches. |
| PCI Interface | 32-bit, 66 MHz, PCI 2.2-compliant - allows direct attachment of legacy NICs, encryption cards, or FPGA co-processors with full bus mastering. |
| Security Engine | Four crypto-channels with AES-256, SHA-256, RSA-2048 - accelerates TLS 1.2 handshake and IPsec ESP/AH at line rate without software overhead. |
| USB Support | Dual-role USB 2.0 (EHCI-compatible) - enables field-upgradeable firmware via USB device mode or peripheral expansion via host mode. |
| Package | 672-pin TBGA (27 mm × 27 mm, 1.0 mm pitch) - provides signal integrity for high-speed DDR and TSEC traces while supporting industrial thermal profiles. |
Pinout & Package
The MPC8347ZUAJDB is housed in a 672-pin TBGA package (27 mm × 27 mm, 1.0 mm pitch) with thermal pad, optimized for DDR-1, TSEC, and PCI signal integrity. Pin assignments follow Freescale's standardized PowerQUICC II Pro layout with dedicated VDD/GND banks, differential clock routing, and I/O voltage domain segregation (VDD = 1.2 V, GVDD = 2.5 V, LVDD/OVDD = 3.3 V).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN | Primary system clock input | Accepts 66 MHz single-ended clock; determines CSB, DDR, and USB PLL frequencies; requires VIH ≥ 2.7 V, tR/tF ≤ 2.3 ns. |
| PORESET | Power-on reset input | Must be asserted ≥32 CLKIN cycles before stable clock; initiates boot sequence and configures CFG_RESET_SOURCE[0:2]. |
| HRESET | Host reset output | Open-drain active-low signal; asserts after PORESET negation; drives external logic and synchronizes peripheral resets. |
| MCK[0:3] | DDR clock outputs | Differential DDR clock pairs; support 200–333 MHz; require matched trace lengths and controlled impedance (50 Ω). |
| MDQ[0:63]/MECC[0:7] | DDR data and ECC bus | 64-bit data + 8-bit ECC; supports full error correction; requires termination to VTT = MVREF ± 40 mV. |
| TSEC0_TXD[0:3]/RXD[0:3] | Gigabit Ethernet PHY interface | RGMII signals for port 0; operate at 1.8 V (LVDD = 2.5 V) or 3.3 V (LVDD = 3.3 V); require <100 ps skew between lanes. |
Key Features
| Feature | Design Value |
|---|---|
| Lockable L1 cache portion | Enables deterministic real-time interrupt response by preventing critical code/data eviction during burst traffic. |
| Programmable DDR timing registers | Allows fine-tuned setup/hold margins for diverse DDR-1 chip vendors and board layouts without hardware revision. |
| PCI-to-memory streaming DMA | Eliminates CPU involvement in large-block transfers between PCI peripherals and DDR, reducing latency by >40% vs. PIO. |
| Hardware CRC generation/checking | Offloads Ethernet frame CRC-32 computation from CPU, enabling wire-speed 1000BASE-T forwarding. |
| GPIO multiplexing with digital filtering | 52 pins shared across I2C, SPI, DUART, timers; on-chip spike rejection prevents false interrupts in electrically noisy environments. |
Applications
| Network Edge Router | Industrial Protocol Gateway |
|---|---|
|
Use Scenario: Aggregating Modbus TCP, PROFINET, and EtherNet/IP traffic from factory-floor PLCs into encrypted IP tunnels. IC Role / Device Role / Timing Role: MPC8347ZUAJDB serves as the secure protocol translation engine, executing real-time packet inspection and TLS 1.2 encryption using its dedicated crypto channels. Use Value: Achieves sub-50 μs latency for time-critical automation packets while maintaining 100 Mbps encrypted throughput via hardware AES-256 acceleration. |
Use Scenario: Bridging legacy RS-485 fieldbus networks to modern cloud SCADA platforms over cellular/Wi-Fi backhaul. IC Role / Device Role / Timing Role: MPC8347ZUAJDB acts as the dual-role USB host/device controller and dual-TSEC endpoint, managing simultaneous serial protocol stacks and WAN uplinks. Use Value: Enables zero-touch firmware updates via USB device mode and seamless failover between LTE and Wi-Fi using independent TSEC MAC-layer control. |
| Secure Wireless Access Point | Medical Imaging Data Concentrator |
|
Use Scenario: Deploying HIPAA-compliant Wi-Fi 5 access points in hospital corridors with WPA3-Enterprise and 802.11i key management. IC Role / Device Role / Timing Role: MPC8347ZUAJDB functions as the IEEE 802.11i security anchor, performing PMK derivation, EAP-TLS certificate validation, and AES-CCM frame encryption in hardware. Use Value: Supports 50+ concurrent clients with full WPA3 handshake completion in <120 ms, eliminating CPU bottlenecks seen in software-only implementations. |
Use Scenario: Consolidating DICOM image streams from MRI, CT, and ultrasound devices into encrypted PACS archives via Gigabit Ethernet. IC Role / Device Role / Timing Role: MPC8347ZUAJDB operates as the DDR-buffered packet assembler, using its 64-bit DDR interface and dual TSECs to sustain 950 Mbps sustained imaging data flow. Use Value: Guarantees lossless transmission of 120 MB DICOM studies within 1.3 seconds using jumbo frames and RMON-based congestion monitoring. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated host processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8349ZUAJDB | Same e300 core and peripheral set, but rated for 667 MHz max (vs. 533 MHz for MPC8347ZUAJDB) and includes enhanced DDR-2 controller. | Better suited for memory-intensive applications requiring >1 GB DDR-2 capacity and higher bandwidth. | Select MPC8349ZUAJDB when DDR-2 migration or >500 MHz sustained core performance is required; MPC8347ZUAJDB remains optimal for cost-sensitive DDR-1 designs. |
| MPC8548CZQAGD | PowerPC e500v2 core (not e300), 1.33 GHz max, integrated SerDes, no hardware security engine, supports DDR2 only. | Lacks integrated crypto acceleration; requires external security IC for IPsec/SSL; targets high-throughput routing over security-offload. | Choose MPC8548CZQAGD for raw packet forwarding >2 Gbps where crypto is handled externally; MPC8347ZUAJDB is preferred when on-die security and DDR-1 compatibility are mandatory. |
Compared with MPC8349ZUAJDB and MPC8548CZQAGD, the MPC8347ZUAJDB uniquely balances DDR-1 compatibility, integrated crypto acceleration, and industrial temperature support in a mature, production-proven platform-making it the optimal choice for secure, cost-sensitive edge infrastructure where DDR-2 migration is not yet justified.
Availability
MPC8347ZUAJDB is available at Aetrix Electronics and suitable for network edge routers, industrial protocol gateways, and secure wireless access points requiring stable component supply and long-term lifecycle assurance.
Supply support for MPC8347ZUAJDB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global leader in secure connectivity solutions for automotive, industrial, and IoT applications, formed from the acquisition of Freescale Semiconductor in 2015.
The MPC8347ZUAJDB belongs to the PowerQUICC™ II Pro family, designed specifically for cost-optimized, secure embedded networking applications requiring integrated processing, connectivity, and hardware-accelerated cryptography.
FAQ
What is the maximum DDR-1 data rate supported by the MPC8347ZUAJDB?
The MPC8347ZUAJDB supports DDR-1 data rates up to 333 MHz in the TBGA package variant, delivering 5.3 GB/s peak bandwidth on the 64-bit interface. This is confirmed in Section 6.2.2 of the MPC8347E Hardware Specifications (Rev. 11), Table 14, which specifies tMCK min = 6 ns (166 MHz clock → 333 MT/s). The PBGA variant is limited to 266 MHz. MPC8347ZUAJDB uses the TBGA package, making 333 MHz its validated maximum DDR-1 speed.
Does the MPC8347ZUAJDB include hardware support for AES-256 encryption?
Yes, the MPC8347ZUAJDB includes a dedicated Advanced Encryption Standard Unit (AESU) that fully implements the Rijndael cipher with key lengths of 128, 192, and 256 bits, supporting ECB, CBC, CCM, and counter (CTR) modes. This is documented in Section 1, "Overview", page 3 of the MPC8347E Hardware Specifications (Rev. 11), under the Security Engine description. The AESU operates independently within one of four crypto-channels, enabling concurrent encryption without CPU load.
Can the MPC8347ZUAJDB operate in both PCI host and PCI agent modes?
Yes, the MPC8347ZUAJDB supports both PCI host bridge and PCI agent modes, configurable via boot-time settings. In host mode, it drives the PCI bus using CLKIN as the primary clock source; in agent mode, it synchronizes to PCI_SYNC_IN. This dual capability is explicitly stated in Section 13, "PCI", page 47, and verified in Table 7 (CLKIN/PCI_CLK AC specs) and Section 5 (RESET Initialization), which defines distinct PORESET assertion timing for each mode.
What is the function of the QUIESCE pin on the MPC8347ZUAJDB?
The QUIESCE pin on the MPC8347ZUAJDB is an active-high input that places the device into a low-power quiescent state, halting all internal clocks except those needed for wake-up detection. It is electrically identical to HRESET and SRESET (per Table 8, RESET Pins DC Characteristics), with VIH ≥ 2.0 V and VIL ≤ 0.8 V. Its use is detailed in Section 5.2, where it appears in timing diagrams alongside HRESET/SRESET assertion sequences for controlled system suspend/resume.
Is the MPC8347ZUAJDB pin-compatible with the MPC8347EA series?
No, the MPC8347ZUAJDB is not pin-compatible with the MPC8347EA series. The MPC8347EA silicon revision (introduced in 2009) introduced electrical and timing changes requiring updated PCB layout, particularly for DDR and TSEC interfaces. As noted in the document's front matter: "For information on revision 3.0 silicon and later versions (for orderable part numbers ending in A or B), see the MPC8347EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications." MPC8347ZUAJDB corresponds to revision 1.1 silicon and uses the original pinout defined in Section 18, "Package and Pin Listings".
MPC8347ZUAJDB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 672-LBGA
- Series:
- MPC83xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e300
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 533MHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 + PHY (2)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- 0°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 672-LBGA (35x35)
- Additional Interfaces:
- DUART, I2C, PCI, SPI
MPC8347ZUAJDB FAQ
1.How can I place an order for MPC8347ZUAJDB through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8347ZUAJDB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8347ZUAJDB reliable?
The price and inventory of MPC8347ZUAJDB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8347ZUAJDB is usually 5 days.
3.What payment methods are accepted for MPC8347ZUAJDB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8347ZUAJDB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8347ZUAJDB?
MPC8347ZUAJDB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8347ZUAJDB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8347ZUAJDB?
For technical support, including MPC8347ZUAJDB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8347ZUAJDB requirements.
6.How does Aetrix verify that MPC8347ZUAJDB is sourced from the original manufacturer or authorized distributors?
All MPC8347ZUAJDB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8347ZUAJDB meets industry standards.
7.What is the process for return or replacement of MPC8347ZUAJDB?
All MPC8347ZUAJDB units undergo pre-shipment inspection (PSI). If there is an issue with MPC8347ZUAJDB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8347ZUAJDB part is unused and in its original packaging.
Return procedure for MPC8347ZUAJDB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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