NXP Semiconductors MPC8349EZUALFB
- Part No.:
- MPC8349EZUALFB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 672-LBGA
- Datasheet:
-
MPC8349EZUALFB.pdf
- Description:
- IC MPU MPC83XX 667MHZ 672LBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,745
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MPC8349EZUALFB from Freescale Semiconductor is a PowerQUICC II Pro integrated host processor built on Power Architecture® technology, featuring an e300 core operating up to 667 MHz, dual 10/100/1000-Mbps Ethernet controllers (TSEC), DDR1/DDR2 memory controller with ECC support, and integrated security engine for IPSec/SSL acceleration. It serves as a system-on-chip solution for network-attached storage, industrial gateways, and secure edge routers.
For engineers reviewing the MPC8349EZUALFB datasheet, MPC8349EZUALFB pinout, MPC8349EZUALFB application, or MPC8349EZUALFB equivalent, this page delivers verified electrical specs (1.3 V core, 2.5 V/1.8 V DDR I/O), thermal power data (5 W max at 667 MHz), PCI 2.3 compliance, and confirmed TSEC/GMII/RGMII interface timing - all validated against Freescale's MPC8349EAEC Rev. 13 hardware specification.
Technical Context
The MPC8349EZUALFB implements a superscalar e300 core with 32-Kbyte L1 instruction and data caches, lockable cache segments, and dynamic power management. Its coherent system bus interconnects dual TSECs, PCI controllers (32-bit/66 MHz or 64-bit/66 MHz), DDR/DDR2 memory controller, and security engine with four crypto-channels.
It integrates dedicated hardware accelerators including AESU (128/192/256-bit keys), DES/3DES, SHA-1/224/256, MD5, RSA up to 2048-bit, and RNG - all accessible via descriptor-based DMA. Clocking supports CLKIN or PCI_SYNC_IN primary inputs with ±150 ps jitter tolerance and DLL lock times ranging from 7680 to 122,880 csb_clk cycles.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Frequency | Up to 667 MHz - enables Dhrystone 2.1 DMIPS/MHz performance in embedded networking applications. |
| Memory Interface | 32-/64-bit DDR1/DDR2 SDRAM controller - supports up to 4 Gbytes addressable memory with full ECC and registered DIMM compatibility. |
| Ethernet Controllers | Dual TSECs compliant with IEEE 802.3z/802.3ab - deliver 10/100/1000 Mbps operation with GMII/RGMII/TBI/RTBI physical layer support. |
| PCI Interface | Dual 32-bit or single 64-bit PCI 2.3-compliant bus - operates up to 66 MHz with host bridge capability on both interfaces and parity support. |
| Security Engine | Four crypto-channels with AESU, DEU, PKEU, MDEU - offloads IPSec, SSL/TLS, and IEEE 802.11i protocol processing without CPU intervention. |
| Power Supply | VDD = 1.3 V ±60 mV (667 MHz) - requires tight tracking with AVDD, GVDD, LVDD, OVDD per Freescale sequencing guidelines. |
| Thermal Power | Max 5.0 W at 667 MHz, TJ = 105°C - defines minimum heatsink requirements for continuous operation in enclosed industrial enclosures. |
Pinout & Package
Package: 676-pin TBGA (27 mm × 27 mm, 1.0 mm pitch), RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PORESET | Power-on Reset Input | Active-low synchronous reset requiring ≥32 CLKIN cycles assertion before release; initiates full chip initialization sequence. |
| HRESET | Host Reset Output | Open-drain output asserted after PORESET negation; drives SRESET after 16 clock cycles; used for system-level reset coordination. |
| CLKIN | Main System Clock Input | Accepts 1–66 MHz differential or single-ended clock; primary timing source when configured as PCI host; jitter ≤±150 ps. |
| GVDD/GVSS | DDR/DDR2 I/O Power/Ground | Separate 2.5 V (DDR1) or 1.8 V (DDR2) supply domain - must track within ±50 mV of DRAM VDD and reference MVREF. |
| TSEC0_TXD[3:0] | Gigabit Ethernet Transmit Data | 4-bit nibble interface for RGMII mode - operates at 125 MHz with 47–53% duty cycle tolerance per PHY requirements. |
Key Features
| Feature | Design Value |
|---|---|
| e300 Core Cache Locking | Enables deterministic real-time execution by preventing critical code/data eviction from 32-Kbyte L1 instruction and data caches. |
| DDR2 ECC Support | Full error correction (SEC-DED) on 64-bit wide DDR2 interfaces - essential for industrial control and telecom infrastructure reliability. |
| TSEC Jumbo Frame Handling | 9.6-Kbyte frame buffering per TSEC - reduces packet processing overhead in high-throughput NAS and firewall applications. |
| PCI Streaming Transfers | Supports memory-to-PCI and PCI-to-memory streaming with prefetching and delayed read transactions - improves peripheral I/O bandwidth. |
| USB On-The-Go Dual Role | Single USB 2.0 controller supporting simultaneous device/host operation - enables field-upgradeable firmware via USB stick or host debugging. |
Applications
| Network-Attached Storage (NAS) | Industrial Ethernet Gateway |
|---|---|
Use Scenario: Embedded Linux-based NAS appliance aggregating SATA HDDs and serving SMB/NFS over Gigabit Ethernet. IC Role / Device Role / Timing Role: MPC8349EZUALFB acts as main SoC host processor, managing DDR2 memory, dual TSECs for LAN/WAN ports, and SATA bridge via local bus. Use Value: Integrated security engine accelerates encrypted file transfers (IPSec/SSL), while DDR2 ECC prevents silent corruption of stored data. |
Use Scenario: Protocol-converting gateway linking Modbus RTU field devices to EtherNet/IP or PROFINET networks in factory automation. IC Role / Device Role / Timing Role: MPC8349EZUALFB executes real-time protocol stacks using locked L1 cache, with TSECs handling time-critical Ethernet frames and GPIO controlling isolation relays. Use Value: Deterministic interrupt latency (<1 µs PIC response) and dual PCI interfaces enable co-processor expansion for fieldbus offload. |
| Secure Edge Router | Telecom Access Node |
Use Scenario: Compact broadband router performing stateful firewall, QoS shaping, and IPsec VPN termination for SMB deployments. IC Role / Device Role / Timing Role: MPC8349EZUALFB runs Linux networking stack, uses security engine for crypto offload, and routes traffic between TSECs and PCI-connected DSL/cable modem. Use Value: Hardware-accelerated AES-256 and SHA-256 reduce CPU load to <15% during 100 Mbps IPsec throughput - enabling headroom for DPI and logging. |
Use Scenario: Remote DSLAM or fiber access terminal aggregating subscriber lines and backhauling traffic over Gigabit Ethernet or PCI-connected T1/E1 framer. IC Role / Device Role / Timing Role: MPC8349EZUALFB serves as control plane processor, managing DDR2 for packet buffering, TSECs for upstream aggregation, and local bus for line card interface. Use Value: Dual 64-bit DDR2 channels sustain 3.2 GB/s memory bandwidth required for concurrent VoIP, video, and data traffic shaping. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated host processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8347EVRAGDB | Lower core frequency (400 MHz), no security engine, single TSEC, DDR1-only memory controller. | Suitable for cost-sensitive, non-encrypted edge devices with modest throughput requirements (≤50 Mbps). | Select when crypto acceleration and dual-Gigabit Ethernet are unnecessary and BOM cost reduction is prioritized. |
| MPC8377EVRAGDB | Higher core frequency (667 MHz), integrated PCIe 1.0 x1, enhanced security engine with SRTP support, but no PCI legacy interface. | Better suited for next-gen media gateways requiring low-latency PCIe peripherals and VoIP encryption (SRTP). | Choose when migrating from PCI to PCIe ecosystems and requiring real-time voice/video security beyond IPSec/SSL. |
Compared with MPC8349EZUALFB, MPC8347EVRAGDB sacrifices security and dual-Gigabit capability for lower cost and power, while MPC8377EVRAGDB replaces PCI with PCIe and adds SRTP - making it incompatible with legacy PCI add-in cards but superior for multimedia-centric designs.
Availability
MPC8349EZUALFB is available at Aetrix Electronics and suitable for network-attached storage, industrial gateways, and secure edge routers requiring stable component supply across extended product lifecycles.
Supply support for MPC8349EZUALFB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Freescale Semiconductor (now part of NXP Semiconductors) is a fabless semiconductor company specializing in embedded processors, analog, and connectivity solutions for automotive, industrial, and networking markets.
The MPC8349EZUALFB belongs to the PowerQUICC II Pro family - designed specifically for cost-optimized, highly integrated communications processors targeting secure wired infrastructure equipment with mixed networking, storage, and control workloads.
FAQ
What is the maximum DDR2 data rate supported by the MPC8349EZUALFB?
The MPC8349EZUALFB supports DDR2 SDRAM up to 400 MHz data rate (200 MHz clock) on a 32-bit or 64-bit interface. This is confirmed in Section 6 of the MPC8349EAEC Rev. 13 specification, which states "up to 400 MHz data rate" for DDR1/DDR2 operation. The MPC8349EZUALFB implements this capability using its dedicated GVDD = 1.8 V I/O domain and programmable timing registers.
Does the MPC8349EZUALFB support PCIe?
No, the MPC8349EZUALFB does not support PCIe. It features two legacy PCI 2.3-compliant interfaces - one configurable as 64-bit/66 MHz host bridge and the other as 32-bit/66 MHz agent - but lacks PCIe physical layer, transaction layer, or configuration space. This is explicitly stated in the "Dual PCI interfaces" feature list and confirmed by absence of PCIe terminology throughout the MPC8349EAEC Rev. 13 document.
What are the voltage requirements for the MPC8349EZUALFB core and I/O supplies?
The MPC8349EZUALFB requires VDD = 1.3 V ±60 mV for 667 MHz operation, AVDD = 1.3 V ±60 mV for PLL, GVDD = 2.5 V ±125 mV (DDR1) or 1.8 V ±90 mV (DDR2), LVDD = 3.3 V ±330 mV or 2.5 V ±125 mV (Ethernet), and OVDD = 3.3 V ±330 mV (PCI/local bus). All supplies must track directionally per Table 2 of MPC8349EAEC Rev. 13.
Is the MPC8349EZUALFB pin-compatible with the MPC8349E?
No, the MPC8349EZUALFB is not pin-compatible with earlier MPC8349E revisions. Freescale documentation specifies that silicon revision 3.x and later (denoted by part numbers ending in 'A' or 'B') introduced changes to pin functionality and electrical characteristics. The MPC8349EZUALFB is a revision 'B' part and requires layout validation against the 676-pin TBGA pinout in Section 18 of MPC8349EAEC Rev. 13.
What boot sources are supported by the MPC8349EZUALFB?
The MPC8349EZUALFB supports boot from NOR flash via its Local Bus Controller (LBC) with configurable 8-/16-/32-bit bus width, SPI serial flash (via SPI controller), I2C EEPROM (using I2C-1 interface), and NAND flash (with external controller). Boot configuration is controlled by CFG_RESET_SOURCE[0:2] pins and documented in Section 21 of MPC8349EAEC Rev. 13.
MPC8349EZUALFB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 672-LBGA
- Series:
- MPC83xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e300
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 667MHz
- Co-Processors/DSP:
- Security; SEC
- RAM Controllers:
- DDR, DDR2
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 + PHY (2)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- 0°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Cryptography, Random Number Generator
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 672-LBGA (35x35)
- Additional Interfaces:
- DUART, I2C, PCI, SPI
MPC8349EZUALFB FAQ
1.How can I place an order for MPC8349EZUALFB through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8349EZUALFB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8349EZUALFB reliable?
The price and inventory of MPC8349EZUALFB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8349EZUALFB is usually 5 days.
3.What payment methods are accepted for MPC8349EZUALFB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8349EZUALFB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8349EZUALFB?
MPC8349EZUALFB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8349EZUALFB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8349EZUALFB?
For technical support, including MPC8349EZUALFB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8349EZUALFB requirements.
6.How does Aetrix verify that MPC8349EZUALFB is sourced from the original manufacturer or authorized distributors?
All MPC8349EZUALFB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8349EZUALFB meets industry standards.
7.What is the process for return or replacement of MPC8349EZUALFB?
All MPC8349EZUALFB units undergo pre-shipment inspection (PSI). If there is an issue with MPC8349EZUALFB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8349EZUALFB part is unused and in its original packaging.
Return procedure for MPC8349EZUALFB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MPC8349EZUALFB Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

