My Inquiry
My Account
NXP Semiconductors MPC8358ZQAGDDA
- Part No.:
- MPC8358ZQAGDDA
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 668-BBGA Exposed Pad
- Datasheet:
-
MPC8358ZQAGDDA.pdf
- Description:
- IC MPU MPC83XX 400MHZ 668BGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,466
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MPC8358ZQAGDDA from NXP Semiconductors (formerly Freescale) is a PowerQUICC II Pro communications processor featuring an e300 PowerPC core operating at up to 400 MHz, integrated QUICC Engine module supporting Ethernet, ATM, HDLC, and POS protocols, and a 32/64-bit DDR/DDR2 SDRAM memory controller. It delivers data plane and control plane functionality for DSLAMs, 3G Node B interface cards, media gateways, and high-end IADs.
For engineers reviewing the MPC8358ZQAGDDA datasheet, MPC8358ZQAGDDA pinout, MPC8358ZQAGDDA application, or MPC8358ZQAGDDA equivalent, key selection criteria include its dual-role processing capability, hardware-accelerated security engine (AES, DES, SHA, RSA), six UCCs with multi-protocol support (10/100/1000 Mbps Ethernet, ATM SAR, HDLC), PCI 2.3 host/agent interface, and flexible local bus controller - all in a 676-pin PBGA package.
Technical Context
The MPC8358ZQAGDDA integrates a superscalar e300 core (Power Architecture™ 603e compatible) with 32 KB instruction and 32 KB data cache, lockable L1 cache, and dynamic power management. Its QUICC Engine comprises two 400 MHz RISC controllers managing six UCCs, enabling concurrent protocol termination and interworking across Ethernet, ATM, HDLC, and POS.
Hardware acceleration includes a dedicated security engine with four crypto-channels supporting IPSec/SSL/TLS offload, a DDR/DDR2 memory controller configurable as 32- or 64-bit at up to 266 MHz data rate, and a PCI 2.3-compliant 32-bit/66 MHz interface with host bridge and agent mode support.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| e300 Core Frequency | Up to 400 MHz - enables real-time packet processing and control-plane execution in telecom infrastructure. |
| Memory Interface | 32/64-bit DDR/DDR2 SDRAM controller - supports up to 4 GB total capacity (4 banks × 1 GB) with full ECC and on-die termination. |
| QUICC Engine UCCs | Six Universal Communication Controllers - provide simultaneous 10/100/1000 Mbps Ethernet (GMII/RGMII/TBI), ATM SAR (622 Mbps), and HDLC (70 Mbps) support. |
| Security Engine | Four crypto-channels with AES-128/192/256, DES/3DES, SHA-1/224/256, MD5, RSA-2048, and RNG - offloads IPSec, SSL/TLS, and IEEE 802.11i® processing. |
| PCI Interface | 32-bit, 66 MHz, PCI 2.3-compliant - operates in host or agent mode with parity, prefetching, and address translation for peripheral bridging. |
| Package | 676-pin PBGA (27 mm × 27 mm, 1.0 mm pitch) - RoHS-compliant, thermally enhanced for industrial temperature operation (–40°C to 105°C). |
| Supply Voltages | VDD = 1.2 V ± 60 mV; GVDD = 1.8 V (DDR2) or 2.5 V (DDR); LVDD/OVDD = 3.3 V ± 330 mV - requires controlled power sequencing (VDD before I/O rails). |
Pinout & Package
Package: 676-pin Plastic Ball Grid Array (PBGA), 27 mm × 27 mm, 1.0 mm ball pitch, RoHS-compliant. Thermal pad on underside for heatsink attachment. Compatible with standard PBGA reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN | Main system clock input | Accepts 1–66.67 MHz reference clock; used for CSB and core PLL when in PCI host mode. |
| PCI_SYNC_IN | PCI synchronization input | Provides clock reference for PCI interface and QUICC Engine when in PCI agent mode. |
| GTX_CLK125 | Gigabit Ethernet reference clock | 125 MHz input for UCC Ethernet transmitters (GMII/RGMII/TBI/RTBI); jitter ≤ ±150 ps. |
| PORESET | Power-on reset input | Active-low asynchronous reset requiring ≥32 CLKIN cycles assertion; initiates boot sequence and configures CFG pins. |
| HRESET | Host reset output | Open-drain signal asserting system-wide reset; drives SRESET after 512 PCI_SYNC_IN cycles. |
| DDR_DQ[0:63] | DDR/DDR2 data bus | 64-bit bidirectional data interface supporting DDR1 (2.5 V SSTL2) or DDR2 (1.8 V SSTL2) with on-die termination. |
| UCC1_TXD/UCC1_RXD | UCC1 serial data I/O | Configurable for 10/100/1000 Mbps Ethernet (MII/RMII/RGMII/GMII/TBI/RTBI) or ATM/HDLC framing. |
Key Features
| Feature | Design Value |
|---|---|
| QUICC Engine Interworking | Hardware-accelerated Ethernet-to-ATM, ATM-to-ATM, and PPP interworking - eliminates software overhead for protocol conversion in media gateways. |
| Security Offload | Dedicated crypto execution units (AESU, DEU, MDEU, PKEU) handling IPSec ESP/AH, TLS record encryption, and IKEv2 - reduces CPU load by >90% for encrypted traffic. |
| Flexible Memory Mapping | Contiguous or discontiguous DDR/DDR2 addressing with 4-bank support and page-mode optimization - enables efficient memory partitioning for real-time OS and packet buffers. |
| PCI Host Bridge | Integrated address translation and coherency enforcement - allows direct memory access between PCI peripherals and DDR without CPU intervention. |
| IEEE 1588 Support | Hardware timestamping in UCCs - provides sub-microsecond time synchronization for TDM-over-packet and precision timing in wireless backhaul. |
Applications
| DSLAM Control & Data Plane | 3G Node B Interface Card |
|---|---|
Use Scenario: Next-generation DSLAM aggregating VDSL2/ADSL2+ lines with VoIP and IPTV services. IC Role / Device Role / Timing Role: MPC8358ZQAGDDA serves as unified control and data plane processor, managing line cards via local bus while forwarding Ethernet/IP traffic through UCCs and PCI-connected switch fabric. Use Value: Integrated QUICC Engine handles ATM-to-Ethernet interworking and QoS scheduling, eliminating need for external protocol converters and reducing BOM cost by 23%. |
Use Scenario: Base station interface card connecting Node B to RNC over ATM or IP transport. IC Role / Device Role / Timing Role: MPC8358ZQAGDDA terminates Iub/Iur interfaces using UCC-based ATM SAR and Ethernet MACs, synchronizes timing via IEEE 1588 hardware timestamps. Use Value: Hardware AES/SHA acceleration secures O&M traffic per 3GPP TS 33.210, achieving 1.2 Gbps encrypted throughput without degrading radio frame processing latency. |
| Media Gateway Controller | High-End Integrated Access Device |
Use Scenario: Session border controller converting SIP/RTCP streams between PSTN and VoIP networks. IC Role / Device Role / Timing Role: MPC8358ZQAGDDA executes signaling stack on e300 core while QUICC Engine performs HDLC framing, TDM slot assignment, and RTP payload processing. Use Value: Six UCCs support concurrent T1/E1 (TDM) and Gigabit Ethernet interfaces, enabling single-chip replacement of dual-processor legacy designs. |
Use Scenario: Carrier-class IAD delivering bonded xDSL, VoIP, and managed Ethernet services to enterprise customers. IC Role / Device Role / Timing Role: MPC8358ZQAGDDA manages DSL PHY via local bus, routes VLAN-tagged traffic via UCC Ethernet ports, and encrypts management traffic using security engine. Use Value: DDR2 memory controller with ECC ensures reliable firmware execution during power brownouts; PCI interface connects to external WAN PHY for redundancy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8360ZQAGDDA | Higher e300 core frequency (up to 533 MHz), additional UCC (seven total), dual DDR2 channels, enhanced security engine with larger IRAM. | Required for >1.5 Gbps aggregate throughput or multi-protocol simultaneous operation beyond MPC8358ZQAGDDA's six-UCC limit. | Select when upgrading existing MPC8358ZQAGDDA designs for higher packet-per-second rates or added TDM channel density. |
| MPC8548CZQAGDDB | e500 core (Power Architecture™ Book III-E), 1.33 GHz max, DDR2-only interface, no QUICC Engine - replaced by SEC and SerDes-based communication accelerators. | Targets next-gen IP-centric infrastructure (LTE EPC, SDN routers); lacks native ATM/HDLC support but offers superior integer performance and PCIe Gen1. | Choose for greenfield designs prioritizing IPv6 forwarding, virtualized CPE, or OpenFlow control plane - not a drop-in replacement. |
Compared with MPC8358ZQAGDDA, MPC8360ZQAGDDA extends bandwidth and protocol concurrency within the same PowerQUICC II Pro architecture, while MPC8548CZQAGDDB represents a generational shift toward packet-processing-centric SoCs with different toolchains and peripheral ecosystems.
Availability
MPC8358ZQAGDDA is available at Aetrix Electronics and suitable for DSLAM control systems, 3G base station interface cards, and media gateway controllers requiring stable component supply across extended product lifecycles.
Supply support for MPC8358ZQAGDDA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and networking applications, with deep heritage in Power Architecture™ processors from its Freescale acquisition.
The MPC8358ZQAGDDA belongs to the PowerQUICC II Pro family, designed specifically for cost-sensitive, high-integration communications infrastructure where deterministic real-time processing, multi-protocol flexibility, and hardware security acceleration are critical.
FAQ
What is the maximum DDR2 data rate supported by the MPC8358ZQAGDDA?
The MPC8358ZQAGDDA supports DDR2 SDRAM at up to 266 MHz data rate (533 MT/s), with 1.8 V SSTL2-compatible I/O, on-die termination, and programmable timing for configurations from 64 Mbit to 1 Gbit ×8/×16 devices. This enables sustained memory bandwidth of 4.2 GB/s in 64-bit mode, sufficient for multi-gigabit packet buffering in media gateways.
Does the MPC8358ZQAGDDA support IEEE 1588 Precision Time Protocol hardware timestamping?
Yes, the MPC8358ZQAGDDA implements IEEE 1588 timestamping in its QUICC Engine UCCs. Each UCC capable of Ethernet operation (UCC1–UCC6) includes dedicated hardware registers to capture precise transmit and receive timestamps with sub-microsecond resolution, essential for TDM circuit emulation and wireless backhaul synchronization.
Can the MPC8358ZQAGDDA operate in both PCI host and PCI agent modes simultaneously?
No, the MPC8358ZQAGDDA operates in either PCI host mode (using CLKIN as primary clock) or PCI agent mode (using PCI_SYNC_IN), selected at boot via CFG_RESET_SOURCE pins. The mode determines clock routing and configuration register mapping; simultaneous dual-mode operation is not supported in hardware or firmware.
What cryptographic algorithms are accelerated by the MPC8358ZQAGDDA security engine?
The MPC8358ZQAGDDA security engine accelerates AES-128/192/256 (ECB/CBC/CCM/counter), DES/3DES (ECB/CBC), SHA-1/224/256, MD5, HMAC-SHA/MD5, RSA-2048, Diffie-Hellman, and elliptic curve cryptography. These are executed in dedicated hardware units (AESU, DEU, MDEU, PKEU) with four independent crypto-channels for concurrent session handling.
Is the MPC8358ZQAGDDA pin-compatible with other PowerQUICC II Pro processors like the MPC8349?
No, the MPC8358ZQAGDDA is not pin-compatible with MPC8349 or MPC8360. While sharing the same 676-pin PBGA footprint, ball assignments differ significantly - especially for DDR/DDR2 signals, UCC I/O, and security engine interfaces - requiring PCB redesign for migration. Functional compatibility exists at the software level via PowerQUICC II Pro SDK.
MPC8358ZQAGDDA Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 668-BBGA Exposed Pad
- Series:
- MPC83xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e300
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 400MHz
- Co-Processors/DSP:
- Communications; QUICC Engine
- RAM Controllers:
- DDR, DDR2
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (1)
- SATA:
- -
- USB:
- USB 1.x (1)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- 0°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 668-PBGA-PGE (29x29)
- Additional Interfaces:
- DUART, HDLC, I2C, PCI, SPI, UART
MPC8358ZQAGDDA FAQ
1.How can I place an order for MPC8358ZQAGDDA through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8358ZQAGDDA on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8358ZQAGDDA reliable?
The price and inventory of MPC8358ZQAGDDA are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8358ZQAGDDA is usually 5 days.
3.What payment methods are accepted for MPC8358ZQAGDDA?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8358ZQAGDDA transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8358ZQAGDDA?
MPC8358ZQAGDDA orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8358ZQAGDDA order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8358ZQAGDDA?
For technical support, including MPC8358ZQAGDDA datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8358ZQAGDDA requirements.
6.How does Aetrix verify that MPC8358ZQAGDDA is sourced from the original manufacturer or authorized distributors?
All MPC8358ZQAGDDA products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8358ZQAGDDA meets industry standards.
7.What is the process for return or replacement of MPC8358ZQAGDDA?
All MPC8358ZQAGDDA units undergo pre-shipment inspection (PSI). If there is an issue with MPC8358ZQAGDDA, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8358ZQAGDDA part is unused and in its original packaging.
Return procedure for MPC8358ZQAGDDA:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MPC8358ZQAGDDA Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
