NXP Semiconductors MPC8358ZQAGDGA

Overview

MPC8358ZQAGDGA from NXP Semiconductors (formerly Freescale) is a PowerQUICC II Pro communications processor featuring an e300 PowerPC core running at 400 MHz, integrated QUICC Engine for multi-protocol packet processing (ATM, Ethernet, HDLC, POS), DDR/DDR2 SDRAM controller (32/64-bit, up to 266 MHz), PCI 2.3 interface (32-bit, 66 MHz), and dedicated security engine supporting AES, DES, SHA, RSA, and RNG. It targets control- and data-plane functions in DSLAMs, Node B base station NICs, media gateways, and high-end IADs.

For engineers reviewing the MPC8358ZQAGDGA datasheet, MPC8358ZQAGDGA pinout, MPC8358ZQAGDGA application, or MPC8358ZQAGDGA equivalent, key selection considerations include e300 core frequency vs. memory bandwidth trade-offs, QUICC Engine UCC protocol allocation (e.g., GMII/RGMII on UCC1/UCC2 vs. MII/RMII on others), DDR1/DDR2 voltage compatibility (GVDD = 2.5 V or 1.8 V), PCI 3.3-V signaling constraints, and security engine crypto-channel concurrency limits.

Technical Context

The MPC8358ZQAGDGA integrates a superscalar e300 core with 32 KB instruction and 32 KB data cache, lockable L1 cache, and dynamic power management. Its QUICC Engine comprises two 400-MHz RISC controllers managing six UCCs-supporting simultaneous 10/100/1000 Mbps Ethernet (GMII/RGMII/TBI/RTBI), ATM SAR up to OC-12 (622 Mbps), POS 124 MultiPHY, HDLC up to 70 Mbps, and IEEE 1588 timestamping.

It features a unified DDR/DDR2 memory controller with full ECC, page-mode support (up to 32 open pages for DDR2), and on-die termination; a PCI 2.3 host/agent interface with parity and address translation; and a security engine with four crypto-channels, PKEU (RSA/DH/ECC), AESU (128/192/256-bit keys), and MDEU (SHA-1/224/256, MD5).

Key Specifications

Pinout & Package

The MPC8358ZQAGDGA is housed in a 676-pin PBGA package (27 mm × 27 mm, 1.0 mm pitch) with thermal lid. Pin assignments follow Freescale's standard PowerQUICC II Pro layout, including dedicated DDR/DDR2 DQ/DQS/CKE/ODT pins, PCI AD[31:0]/C/BE[3:0] bus, six UCC serial interface groups (TxD/RxD/CLK/FS), and QUICC Engine-specific signals (QE_CLK, QE_RST, IRAM_ADDR).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar communications processor applications.

Compared with MPC8360ZQAGDGA, MPC8358ZQAGDGA offers lower power (2.5 W typical vs. 3.8 W) and cost while retaining full QUICC Engine protocol coverage for ATM/Ethernet convergence; versus MPC8548CZQAGDGA, it provides indispensable legacy telecom acceleration absent in Power Architecture e500-based successors.

Availability

MPC8358ZQAGDGA is available at Aetrix Electronics and suitable for DSLAM control plane, 3G Node B NIC, media gateway signaling, high-end IAD VoIP platform, and telecom infrastructure requiring stable component supply across extended product lifecycles.

Supply support for MPC8358ZQAGDGA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors, formed from the acquisition of Freescale Semiconductor in 2015, is a global leader in secure connectivity solutions for automotive, industrial, and networking applications.

The MPC8358ZQAGDGA belongs to the PowerQUICC II Pro family, designed specifically for cost-sensitive, highly integrated communications infrastructure requiring simultaneous control-plane processing and hardware-accelerated data-plane protocol handling.

FAQ

What is the maximum DDR2 data rate supported by the MPC8358ZQAGDGA?

The MPC8358ZQAGDGA supports DDR2 SDRAM at up to 266 MHz data rate (533 MT/s), with a 32- or 64-bit interface, four memory banks, and full ECC capability. This enables sustained memory bandwidth of up to 4.2 GB/s in 64-bit configuration, sufficient for multi-service media gateway packet buffering and firmware execution. The DDR2 I/O uses 1.8-V SSTL2 signaling with on-die termination and external driver impedance calibration.

Does the MPC8358ZQAGDGA support IEEE 1588 Precision Time Protocol hardware timestamping?

Yes, the MPC8358ZQAGDGA provides hardware-assisted IEEE 1588 timestamping within its QUICC Engine UCC Ethernet controllers. Timestamps are inserted into or extracted from Ethernet frames at the MAC layer with sub-100 ns precision, enabling synchronization in wireless backhaul and packet-based fronthaul applications. This functionality operates independently of the e300 core, reducing software latency and jitter in time-critical deployments.

Can the MPC8358ZQAGDGA operate in PCI agent mode with a 32-bit, 33 MHz PCI bus?

Yes, the MPC8358ZQAGDGA supports PCI agent mode on its 32-bit PCI interface at frequencies up to 66 MHz, including 33 MHz operation. In agent mode, it responds to PCI bus master requests, supports memory-mapped I/O, and handles PCI-to-memory streaming with prefetching. The interface is strictly 3.3-V compatible and requires proper termination and slot power sequencing per PCI Specification Revision 2.3.

What cryptographic algorithms are accelerated by the security engine in the MPC8358ZQAGDGA?

The MPC8358ZQAGDGA security engine accelerates AES (128/192/256-bit keys in ECB/CBC/CCM/counter modes), DES/3DES, SHA-1/224/256, MD5, HMAC-SHA/MD5, RSA up to 2048 bits, Diffie-Hellman, and elliptic curve cryptography. It includes a dedicated random number generator and four crypto-channels capable of concurrent operations, delivering line-rate IPSec and SSL/TLS offload for telecom edge devices.

Is the MPC8358ZQAGDGA pin-compatible with other PowerQUICC II Pro processors like the MPC8349?

No, the MPC8358ZQAGDGA is not pin-compatible with the MPC8349 or other PowerQUICC II Pro variants. It uses a 676-pin PBGA package with unique pin assignments for its six UCCs, dual DDR/DDR2 interface, and enhanced security engine signals. Migration from MPC8349 requires PCB redesign due to differences in ball count, power domain layout (e.g., separate GVDD for DDR2), and QUICC Engine signal routing.