NXP Semiconductors MPC8379ECVRALG
- Part No.:
- MPC8379ECVRALG
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 689-BBGA Exposed Pad
- Datasheet:
-
MPC8379ECVRALG.pdf
- Description:
- IC MPU MPC83XX 667MHZ PBGA689
- Quantity:
- Payment:

- Shipping:

Inventory:4,011
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Product details
Overview
MPC8379ECVRALG from NXP Semiconductors (formerly Freescale) is a PowerQUICC® II Pro communications processor featuring an e300 core built on Power Architecture® technology, dual Gigabit Ethernet controllers, integrated PCI Express® (x1/x2), Serial-ATA I/II (1.5/3.0 Gbps), and optional security engine - deployed in wireless access points, network-attached storage, and SMB routers.
For engineers reviewing the MPC8379ECVRALG datasheet, MPC8379ECVRALG pinout, MPC8379ECVRALG application, or MPC8379ECVRALG equivalent, key selection criteria include 800 MHz e300 core performance, 689-pin PBGA package compatibility, SATA II + PCIe integration, IEEE 1588 timing support, and E-version cryptographic acceleration (AES-256, SHA-512, RSA).
Technical Context
The MPC8379ECVRALG implements a superscalar 32-bit e300 core with dual integer units and a floating-point unit, operating at 400–800 MHz with 32 KB L1 instruction and data cache (parity-protected). It supports DDR1/DDR2 memory up to 400 MHz data rate via a configurable 32-/64-bit controller.
It integrates two independent Gigabit Ethernet MACs with RGMII/RTBI/SGMII/MII/RMII PHY interfaces, one USB 2.0 host/device controller, two I²C buses, DUART, SPI, and a 4-channel DMA engine - all coordinated by an enhanced local bus controller supporting NAND/NOR boot.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| e300 Core Speed | 400–800 MHz; enables real-time packet processing and application-layer services in edge networking devices. |
| L1 Cache | 32 KB instruction + 32 KB data with parity; reduces memory latency and improves deterministic throughput for control-plane tasks. |
| Ethernet Interfaces | Dual 10/100/1000 Mbps MACs with RGMII/SGMII/MII support; allows concurrent WAN/LAN or LAN/LAN bridging without external PHYs. |
| SATA Support | Four SATA 2.0 ports (1.5/3.0 Gbps) with integrated PHY; eliminates need for discrete SATA bridge ICs in NAS and media server designs. |
| PCI Express | Two lanes configurable as x1 + x1 or single x2 link; provides low-latency expansion for Wi-Fi radios or encryption co-processors. |
| Security Engine | Hardware-accelerated AES-256, SHA-512, RSA, DES/3DES, and HMAC; offloads TLS/IPsec processing from main CPU in secure gateway applications. |
| Memory Interface | 32-/64-bit DDR1/DDR2 up to 400 MHz; supports up to 2 GB system RAM with ECC-capable controllers for industrial reliability. |
Pinout & Package
Package: 689-ball Thin Enhanced Plastic Ball Grid Array (Te PBGA), 27 mm × 27 mm, 1.0 mm ball pitch, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN | Reference clock input | Accepts 33–100 MHz differential or single-ended clock for system timing synchronization. |
| RST_IN | Asynchronous reset input | Active-low signal initiating full chip reset including memory controller and peripheral state machines. |
| DDR_DQ[0:63] | DDR data bus | 64-bit bidirectional data interface supporting DDR1/DDR2 burst transfers at up to 400 MT/s. |
| ETH0_TXD[0:3] | Gigabit Ethernet 0 transmit data | 4-bit nibble for RGMII transmit path; requires matched trace length to PHY for sub-nanosecond skew control. |
| SATA_TXP/N[0:3] | SATA differential transmit pairs | Four high-speed serial lanes (SATA0–SATA3) with integrated 1.5/3.0 Gbps transceivers and impedance-matched routing. |
| PCIe_RXP/N[0:1] | PCI Express receive differential pairs | Two dedicated x1 PCIe lanes supporting Gen1 (2.5 GT/s); compatible with standard PCIe endpoint enumeration. |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol support | Hardware timestamping in Ethernet MACs enables sub-microsecond time synchronization for industrial automation and telecom backhaul. |
| NAND flash boot capability | Direct execution from NAND avoids boot ROM dependency and reduces BOM cost in headless embedded systems. |
| Integrated SATA PHY | Eliminates external SATA transceivers and level shifters, reducing PCB layer count and signal integrity complexity. |
| PCI Express revision 1.0a compliance | Guarantees interoperability with standard PCIe switches, Wi-Fi modules, and FPGA-based accelerators. |
| Enhanced interrupt controller (MPIC) | Supports 128 vectored interrupts with priority arbitration and masking - critical for real-time response in multi-service gateways. |
Applications
| Wireless Access Point | Network-Attached Storage |
|---|---|
Use Scenario: Concurrent handling of 802.11n/ac client traffic, QoS scheduling, firewall/NAT, and captive portal services. IC Role / Device Role / Timing Role: Main system-on-chip managing RF interface coordination, packet forwarding, and storage I/O scheduling. Use Value: Dual Gigabit Ethernet + four SATA ports enable simultaneous upstream/downstream traffic and direct HDD attachment without bridge chips. | Use Scenario: Multi-bay RAID enclosure with file sharing, DLNA streaming, and backup services over SMB/CIFS/NFS protocols. IC Role / Device Role / Timing Role: Central controller orchestrating SATA disk I/O, network protocol stack, and USB mass storage interface. Use Value: Integrated SATA 2.0 PHY and hardware RAID assist reduce latency and CPU load during sequential read/write operations. |
| SMB Router/Firewall | Industrial Media Gateway |
Use Scenario: Stateful packet inspection, VLAN routing, VoIP signaling, and dynamic DNS across dual WAN/LAN interfaces. IC Role / Device Role / Timing Role: Security-aware network processor executing IPsec tunneling and deep packet inspection in parallel with forwarding. Use Value: On-die AES-256 and SHA-512 acceleration enables line-rate 100 Mbps IPsec throughput without software overhead. | Use Scenario: Video transcoding gateway aggregating RTSP streams from IP cameras and repackaging for HLS/DASH delivery. IC Role / Device Role / Timing Role: Real-time media scheduler interfacing with external DSP/FPGA while maintaining precise AV sync via IEEE 1588 timestamps. Use Value: Hardware timestamping on both Ethernet MACs ensures frame-accurate lip-sync and jitter-free playback across heterogeneous networks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8377ECVRALG | Two SATA ports (vs. four), no PCIe; same e300 core, memory, and Ethernet specs. | Suitable for cost-sensitive NAS with ≤2 drives or single-interface routers. | Select when PCIe expansion and quad-SATA are unnecessary to reduce BOM and layout complexity. |
| MPC8378ECVRALG | Two PCIe lanes (x1/x1), two SATA ports, no security engine (no 'E' suffix); identical package and pinout. | Preferred for non-encrypted wireless infrastructure where PCIe-to-WiFi co-location is required. | Choose when cryptographic acceleration is not needed but PCIe flexibility and dual-SATA suffice. |
Compared with MPC8377ECVRALG and MPC8378ECVRALG, the MPC8379ECVRALG uniquely delivers four SATA ports plus PCIe and full security engine - making it the only variant enabling encrypted, high-density storage + expansion in a single 689-pin footprint.
Availability
MPC8379ECVRALG is available at Aetrix Electronics and suitable for wireless access points, network-attached storage systems, and SMB routers requiring stable component supply, long-term lifecycle assurance, and industrial-grade thermal performance.
Supply support for MPC8379ECVRALG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with heritage in Power Architecture® and communications processors.
The MPC8379ECVRALG belongs to the PowerQUICC® II Pro family - designed specifically for cost-sensitive, highly integrated networking edge devices requiring dual-GbE, storage I/O, and hardware security in a single SoC.
FAQ
What is the maximum operating frequency of the MPC8379ECVRALG?
The MPC8379ECVRALG features an e300 core rated for operation up to 800 MHz. This speed is validated under specified thermal and voltage conditions per the official NXP datasheet MPC837XFFS REV 1. The device supports multiple speed grades (400/533/667/800 MHz), with MPC8379ECVRALG configured for 800 MHz operation. System design must ensure adequate power delivery and heat dissipation to sustain this frequency reliably.
Does the MPC8379ECVRALG include hardware cryptographic acceleration?
Yes, the MPC8379ECVRALG includes a full-featured integrated security engine, indicated by the 'E' in its part number. It supports AES-256, SHA-512, RSA, DES/3DES, HMAC, and more - all implemented in dedicated hardware blocks. This enables line-rate IPsec and TLS offload without consuming e300 core cycles, a capability confirmed in the MPC837XFFS documentation and verified in reference designs for secure SMB gateways.
How many SATA interfaces does the MPC8379ECVRALG support?
The MPC8379ECVRALG supports four independent SATA 2.0 interfaces, each capable of 1.5 Gbps or 3.0 Gbps operation with integrated PHYs. This is explicitly stated in the family comparison table and functional specification section of the MPC837XFFS datasheet. No external SATA bridge IC is required, simplifying board layout and improving signal integrity for multi-drive NAS implementations.
Is the MPC8379ECVRALG pin-compatible with other MPC837x variants?
Yes, the MPC8379ECVRALG shares the identical 689-ball Te PBGA package and pinout with MPC8377ECVRALG and MPC8378ECVRALG. All three variants use the same mechanical footprint, ball map, and power/ground assignment. However, functionality differs per pin - for example, SATA and PCIe signals are allocated differently across variants - so firmware and schematic design must match the selected part's feature set.
What Ethernet PHY interfaces are supported by the MPC8379ECVRALG?
The MPC8379ECVRALG supports RGMII, SGMII, RTBI, MII, and RMII interfaces across its dual Gigabit Ethernet MACs. These modes are selectable per port via configuration registers and strap pins. RGMII is commonly used for direct connection to external PHYs, while SGMII enables direct chip-to-chip links with switches or SerDes devices - all confirmed in the MPC837XFFS electrical characteristics and interface timing tables.
MPC8379ECVRALG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 689-BBGA Exposed Pad
- Series:
- MPC83xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e300c4s
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 667MHz
- Co-Processors/DSP:
- Security; SEC 3.0
- RAM Controllers:
- DDR, DDR2
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- SATA 3Gbps (4)
- USB:
- USB 2.0 + PHY (1)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Cryptography, Random Number Generator
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 689-TEPBGA II (31x31)
- Additional Interfaces:
- DUART, I2C, MMC/SD, PCI, SPI
MPC8379ECVRALG FAQ
1.How can I place an order for MPC8379ECVRALG through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8379ECVRALG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8379ECVRALG reliable?
The price and inventory of MPC8379ECVRALG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8379ECVRALG is usually 5 days.
3.What payment methods are accepted for MPC8379ECVRALG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8379ECVRALG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8379ECVRALG?
MPC8379ECVRALG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8379ECVRALG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8379ECVRALG?
For technical support, including MPC8379ECVRALG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8379ECVRALG requirements.
6.How does Aetrix verify that MPC8379ECVRALG is sourced from the original manufacturer or authorized distributors?
All MPC8379ECVRALG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8379ECVRALG meets industry standards.
7.What is the process for return or replacement of MPC8379ECVRALG?
All MPC8379ECVRALG units undergo pre-shipment inspection (PSI). If there is an issue with MPC8379ECVRALG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8379ECVRALG part is unused and in its original packaging.
Return procedure for MPC8379ECVRALG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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