NXP Semiconductors MPC8379EVRAGDA
- Part No.:
- MPC8379EVRAGDA
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- -
- Datasheet:
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MPC8379EVRAGDA.pdf
- Description:
- POWERQUICC, 32 BIT POWER ARCH SO
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Product details
Overview
MPC8379EVRAGDA from NXP Semiconductors (formerly Freescale) is a PowerQUICC II Pro communications processor integrating an e300c4s Power Architecture core, dual enhanced three-speed Ethernet controllers (eTSEC), DDR1/DDR2 memory controller, PCI 2.3 interface, USB 2.0 dual-role controller, SATA 2.5 controller, and optional SEC 3.0 security engine - designed for embedded networking and industrial control applications including VPN routers, intelligent NICs, and industrial controllers.
For engineers reviewing the MPC8379EVRAGDA datasheet, MPC8379EVRAGDA pinout, MPC8379EVRAGDA application, or MPC8379EVRAGDA equivalent, this page delivers verified technical context on its e300c4s CPU architecture, 667 MHz core frequency, dual RGMII/MII/RMII Ethernet interfaces, 4-port SATA support, and SEC 3.0 cryptographic acceleration - enabling accurate selection for cost-sensitive, low-power, high-integration host processor designs.
Technical Context
The MPC8379EVRAGDA implements a superscalar e300c4s core with 32 KB instruction and 32 KB data L1 caches, floating-point unit, and two integer units - operating at up to 667 MHz with 1.0 V ±50 mV core supply. Its DDR1/DDR2 memory controller supports 32-/64-bit interfaces at up to 400 MHz data rate with four chip selects and auto-refresh capability.
It integrates two IEEE 802.3-compliant eTSECs supporting RGMII, RMII, MII, and RTBI modes; a PCI 2.3-compliant 32-bit/66 MHz controller in host or agent mode; four SATA 2.5 ports (1.5/3.0 Gb/s); and an optional SEC 3.0 engine accelerating DES, 3DES, AES, SHA-1, and MD5 - all coordinated via a 4-channel DMA and IPIC interrupt controller.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | e300c4s Power Architecture core with FPU and dual integer units - enables deterministic real-time processing in networking stacks and protocol offload. |
| Max Core Frequency | 667 MHz at 1.0 V ±50 mV - delivers Dhrystone 2.1 DMIPS/MHz performance suitable for multi-service edge routing. |
| Memory Interface | DDR1/DDR2 SDRAM controller with 32-/64-bit bus, 400 MHz data rate, 4 chip selects - supports up to 4-Gbit DDR2 devices for scalable system memory. |
| Ethernet Interfaces | Dual eTSECs compliant with IEEE 802.3/802.3u/802.3ab/1588 - each configurable as RGMII, RMII, MII, or RTBI for flexible PHY integration and PTP time synchronization. |
| SATA Ports | Four SATA 2.5 controllers (1.5/3.0 Gb/s) with native command queuing and hot-plug - enables direct storage connectivity without external bridge ICs. |
| Security Engine | Optional SEC 3.0 crypto accelerator supporting DES, 3DES, AES, SHA-1, MD5 - offloads IPSec/IKE and 802.11i data-plane encryption from main CPU. |
| PCI Interface | 32-bit/66 MHz PCI 2.3 controller with host/agent mode support and 5-master arbitration - provides legacy expansion and inter-processor communication capability. |
Pinout & Package
The MPC8379EVRAGDA is housed in a 783-pin PBGA package (35 mm × 35 mm, 1.0 mm pitch) with thermal lid and RoHS-compliant finish. Pin assignments are defined per Table 21–1 in MPC8379EEC Rev. 8 (pp. 78–103), including dedicated banks for DDR, eTSEC, PCI, SATA, and I/O power domains.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD / AVDD | Core & PLL power supply | 1.0 V ±50 mV input required before I/O rails - violation risks latch-up or boot failure during power sequencing. |
| GVDD | DDR I/O supply | 2.5 V ±125 mV (DDR1) or 1.8 V ±90 mV (DDR2) - must track VDD directionally; mismatch causes signal integrity loss or timing violations. |
| LVDD[1,2] | eTSEC I/O supply | 3.3 V ±165 mV or 2.5 V ±125 mV - configures RGMII voltage level and determines compatible PHY families (e.g., Marvell 88E6060 vs. TI DP83865). |
| OVDD | PCI/local bus/I2C/JTAG supply | 3.3 V ±165 mV - powers all control-plane peripherals; undershoot beyond –0.3 V risks JTAG debug port corruption. |
| HRESET / PORESET | Reset assertion inputs | HRESET active-low open-drain output; PORESET active-low input - requires ≥32 tCLKIN assertion before clock stabilization for reliable boot initialization. |
| CLKIN / PCI_CLK | Main clock input | 25–66.666 MHz differential-capable single-ended input - jitter ≤±150 ps ensures stable PLL lock for CSB/DDR clock generation. |
Key Features
| Feature | Design Value |
|---|---|
| USB 2.0 Dual-Role Controller | EHCI-compatible host + device mode with ULPI PHY interface - enables firmware update via USB device mode and peripheral attachment via host mode without external hub logic. |
| Enhanced Local Bus Controller (eLBC) | 32-bit bus running up to 133 MHz with NAND Flash control machine and 8 memory banks - eliminates glue logic for NOR/NAND/SRAM/DRAM interfacing in printer SoM designs. |
| Integrated Programmable Interrupt Controller (IPIC) | 42 total interrupt sources (8 external + 34 internal) with MPC8260-compatible programming model - simplifies migration from legacy PowerQUICC II platforms. |
| Dual I2C Controllers | Multi-master synchronous buses supporting EEPROM, RTC, and sensor configuration - allows independent bus arbitration for thermal monitoring and power management subsystems. |
| Power Management Controller (PMC) | PCI D0–D3hot state support, Wake-on-LAN, USB, GPIO, and PME detection - enables low-power sleep states in network access servers with rapid resume capability. |
Applications
| VPN Router | Industrial Controller |
|---|---|
Use Scenario: Edge-site secure tunnel termination handling multiple concurrent IPSec sessions with QoS-aware packet forwarding. IC Role / Device Role / Timing Role: Main CPU executing Linux-based routing stack while SEC 3.0 accelerates ESP/AH encryption/decryption in hardware. Use Value: 667 MHz e300c4s core sustains >200 Mbps encrypted throughput; dual eTSECs provide WAN/LAN separation with IEEE 1588 timestamping for SLA monitoring. |
Use Scenario: Real-time motion control in CNC machines requiring deterministic I/O response and fieldbus coexistence (e.g., EtherCAT + Modbus TCP). IC Role / Device Role / Timing Role: Host processor managing EtherCAT master stack, local bus-connected FPGA I/O, and SATA-booted firmware image. Use Value: eLBC's 133 MHz local bus drives FPGA configuration registers with <100 ns latency; dual eTSECs isolate control traffic from diagnostic traffic via RGMII+MII split. |
| Intelligent NIC | Network Access Server (NAS) |
Use Scenario: Offloading TCP/IP checksum, VLAN tagging, and large-send segmentation from host CPU in server blade environments. IC Role / Device Role / Timing Role: Dedicated I/O processor bridging PCIe-equivalent PCI bus to dual Ethernet PHYs and DDR2 memory for packet buffering. Use Value: 4-channel DMA enables zero-copy packet forwarding between eTSECs and DDR2; USB 2.0 device mode permits out-of-band firmware updates without host intervention. |
Use Scenario: Multi-user broadband aggregation platform supporting DSL, cable, and wireless backhaul with AAA authentication and policy enforcement. IC Role / Device Role / Timing Role: Central host CPU running embedded Linux, managing four SATA drives for user profile storage and logging, plus dual eTSECs for upstream/downstream aggregation. Use Value: Four SATA 2.5 ports eliminate SATA bridge ICs - reducing BOM cost and PCB area; SEC 3.0 accelerates RADIUS/TACACS+ cryptographic operations for concurrent user sessions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8377EVRAGDA | Two SGMII ports instead of four SATA; no SATA support; identical e300c4s core and eTSECs. | Better suited for fiber-uplink switches where SGMII PHYs replace copper Ethernet; unsuitable for storage-integrated NAS or DVR designs. | Select when optical uplinks are required and local storage is handled externally - avoids over-specifying SATA PHY resources. |
| MPC8378EVRAGDA | Two PCI Express lanes instead of four SATA; retains same DDR, eTSEC, USB, and security features. | Optimized for PCIe endpoint expansion (e.g., adding Wi-Fi or cellular modems); lacks native mass storage interface. | Choose for modular I/O extension where PCIe peripherals dominate over direct SATA storage - preserves software compatibility while upgrading interconnect bandwidth. |
Compared with MPC8377EVRAGDA and MPC8378EVRAGDA, the MPC8379EVRAGDA uniquely delivers four integrated SATA 2.5 controllers - making it the only variant in the MPC837xE family capable of standalone multi-drive NAS or DVR functionality without bridge ICs, while maintaining full backward compatibility with PowerQUICC II Pro software and pinout.
Availability
MPC8379EVRAGDA is available at Aetrix Electronics and suitable for VPN routers, industrial controllers, intelligent NICs, and network access servers requiring stable component supply across extended temperature ranges (–40°C to 125°C junction).
Supply support for MPC8379EVRAGDA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep heritage in Power Architecture processors from its Freescale acquisition.
The MPC8379EVRAGDA belongs to the PowerQUICC II Pro family - engineered specifically for cost-optimized, low-power embedded networking applications demanding integrated Ethernet, storage, security, and real-time control in a single-chip solution.
FAQ
What is the maximum DDR2 data rate supported by the MPC8379EVRAGDA?
The MPC8379EVRAGDA DDR1/DDR2 memory controller supports up to 400 MHz data rate, corresponding to DDR2-800 operation. This is achieved with GVDD = 1.8 V ±90 mV and requires proper termination, layout-controlled trace lengths, and validated DDR2 SDRAM parts rated for 400 MHz operation. The controller supports 32- or 64-bit interfaces and up to four chip selects, enabling configurations from 512 MB to 8 GB depending on density and bus width. MPC8379EVRAGDA design guides specify strict setup/hold timing margins relative to CSB clock for reliable initialization.
Does the MPC8379EVRAGDA include a built-in security engine?
Yes, the "E" suffix in MPC8379EVRAGDA explicitly denotes inclusion of the SEC 3.0 security engine. It provides hardware acceleration for DES, 3DES, AES, SHA-1, and MD5 algorithms via dedicated crypto execution units - offloading CPU-intensive operations from the e300c4s core. The engine supports one crypto-channel with multi-command descriptor chains and is optimized for IPSec, IEEE 802.11i, and iSCSI protocol stacks. MPC8379EVRAGDA's SEC 3.0 is enabled by default in boot ROM and configurable via U-Boot environment variables.
What Ethernet PHY interfaces does the MPC8379EVRAGDA support?
The MPC8379EVRAGDA dual eTSECs support RGMII, RMII, MII, and RTBI physical layer interfaces - selectable per channel via strap pins and software configuration. RGMII is commonly used with Gigabit PHYs like the Marvell 88E1111, while MII/RMII suit 10/100 Mbps PHYs such as the Micrel KS8721. RTBI mode enables connection to XAUI-capable SerDes PHYs. MPC8379EVRAGDA requires LVDD = 2.5 V or 3.3 V to match the selected PHY's I/O voltage, and its MII management interface (MDIO/MDC) controls external PHY registers directly.
Can the MPC8379EVRAGDA operate in PCI host mode?
Yes, the MPC8379EVRAGDA PCI controller fully supports PCI host mode, using CLKIN as the primary clock source and providing 32-bit/66 MHz operation with on-chip arbitration for up to five external masters. In host mode, it drives PCI bus signals including FRAME#, IRDY#, and TRDY#, and supports PCI Power Management 1.2 D0–D3hot states. MPC8379EVRAGDA's host-mode configuration is set via CFG_RESET_SOURCE straps and validated in early boot - enabling use as a root complex in legacy expansion systems.
What is the thermal design power (TDP) of the MPC8379EVRAGDA at 667 MHz?
At 667 MHz core frequency and 333 MHz CSB/DDR frequency, the MPC8379EVRAGDA exhibits typical application power dissipation of 2.1 W at Tj = 65°C and 3.3 W at Tj = 125°C, excluding I/O supply contributions. Total system power - including GVDD, LVDD, and OVDD rails - reaches ~4.1 W under worst-case conditions. MPC8379EVRAGDA requires a thermal pad on the PBGA package bottom and a minimum 4-layer PCB with dedicated ground/power planes and ≥2 oz copper for reliable operation above 65°C ambient.
MPC8379EVRAGDA Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- -
- Series:
- *
- Packaging:
- Bulk
- Product Status:
- Active
- Core Processor:
- -
- Number of Cores/Bus Width:
- -
- Speed:
- -
- Co-Processors/DSP:
- -
- RAM Controllers:
- -
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- -
- SATA:
- -
- USB:
- -
- Voltage - I/O:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Additional Interfaces:
- -
MPC8379EVRAGDA FAQ
1.How can I place an order for MPC8379EVRAGDA through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8379EVRAGDA on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8379EVRAGDA reliable?
The price and inventory of MPC8379EVRAGDA are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8379EVRAGDA is usually 5 days.
3.What payment methods are accepted for MPC8379EVRAGDA?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8379EVRAGDA transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8379EVRAGDA?
MPC8379EVRAGDA orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8379EVRAGDA order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8379EVRAGDA?
For technical support, including MPC8379EVRAGDA datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8379EVRAGDA requirements.
6.How does Aetrix verify that MPC8379EVRAGDA is sourced from the original manufacturer or authorized distributors?
All MPC8379EVRAGDA products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8379EVRAGDA meets industry standards.
7.What is the process for return or replacement of MPC8379EVRAGDA?
All MPC8379EVRAGDA units undergo pre-shipment inspection (PSI). If there is an issue with MPC8379EVRAGDA, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8379EVRAGDA part is unused and in its original packaging.
Return procedure for MPC8379EVRAGDA:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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