NXP Semiconductors MPC8560CPX667JB

Overview

MPC8560CPX667JB from NXP (formerly Freescale) is a PowerQUICC III integrated communications processor featuring an e500 core running at 667 MHz, 256 KB on-chip L2 cache/SRAM, dual 10/100/1000 Mbps Ethernet controllers (TSECs), DDR-1 SDRAM controller (64-bit, up to 333 MHz), PCI/PCI-X (64-bit, 133 MHz), and 8-bit RapidIO interface - deployed in carrier-grade networking line cards and telecom infrastructure equipment.

For engineers reviewing the MPC8560CPX667JB datasheet, MPC8560CPX667JB pinout, MPC8560CPX667JB application, or MPC8560CPX667JB equivalent, key selection considerations include its 667 MHz e500 core frequency, 256 KB configurable L2 cache/SRAM, dual TSEC support with RGMII/TBI/GMII, DDR-1 memory controller timing compliance, and 783-pin FC-PBGA package mechanical constraints.

Technical Context

The MPC8560CPX667JB implements a Book E–enhanced 32-bit e500 core with 32 KB L1 instruction and 32 KB L1 data caches (parity-protected), MMU optimized for embedded real-time OS environments, and performance monitor unit supporting eight 32-bit event counters. Its CPM subsystem operates at up to 333 MHz and handles serial protocols including HDLC, ATM via UTOPIA, and ISDN via TDM interfaces.

System-level integration includes an OCeaN four-port crossbar switch fabric for packet reordering and starvation avoidance, a four-channel DMA controller with scatter-gather and misaligned transfer support, and dual TSECs compliant with IEEE 802.3z/ab/ac standards - all coordinated through a coherency-enabled Core Complex Bus (CCB) operating at 333 MHz.

Key Specifications

Pinout & Package

The MPC8560CPX667JB is housed in a 783-ball Fine-Pitch Column Grid Array (FC-PBGA) package with 1.0 mm ball pitch, 35 mm × 35 mm body size, and thermal pad exposed on underside for heatsink mounting. Pin assignments follow Freescale's standardized PowerQUICC III ballout layout with dedicated voltage domains (VDD = 1.2 V core, GVDD = 2.5 V DDR, LVDD = 2.5/3.3 V Ethernet, OVDD = 3.3 V I/O).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar integrated communications processor applications.

Compared with MPC8560CPX667JB, MPC8560CZQ667LB offers identical functionality with RoHS compliance and enhanced thermal reliability, while MPC8548CZQ800B trades RapidIO for PCIe and DDR-2 to target next-generation control-plane acceleration - making the original part optimal for established RapidIO-based telecom platforms.

Availability

MPC8560CPX667JB is available at Aetrix Electronics and suitable for carrier-grade networking line cards, wireless infrastructure baseband units, and telecom media gateways requiring stable component supply across long product lifecycles.

Supply support for MPC8560CPX667JB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors (formerly Freescale Semiconductor) is a global leader in secure connectivity solutions for automotive, industrial, and networking applications, with deep expertise in Power Architecture™-based processors.

The MPC8560CPX667JB belongs to the PowerQUICC III family - designed specifically for high-performance, low-latency communications infrastructure requiring integrated packet processing, protocol acceleration, and multi-standard interconnect.

FAQ

What is the maximum DDR-1 data rate supported by the MPC8560CPX667JB?

The MPC8560CPX667JB supports DDR-1 SDRAM at up to 333 MHz data rate (166 MHz clock), delivering 5.3 GB/s peak bandwidth across its 64-bit interface. This is confirmed in Section 4 of the MPC8560 Hardware Specifications Rev. 4.2, which specifies programmable timing parameters for DDR-1 devices with x8/x16 configurations and full ECC support. The MPC8560CPX667JB requires 2.5 V SSTL2-compatible I/O and external MVREF = GVDD/2.

Does the MPC8560CPX667JB support PCIe, or only PCI/PCI-X?

The MPC8560CPX667JB supports PCI 2.2 and PCI-X 1.0 only - it does not include a PCIe controller. Its 64-bit PCI/PCI-X interface operates up to 133 MHz in PCI-X mode and supports dual-address cycles, split transactions, and memory prefetching. PCIe capability was introduced in later PowerQUICC III derivatives like the MPC8548, but the MPC8560CPX667JB's interconnect roadmap centers on PCI-X and RapidIO.

How many independent Ethernet MACs does the MPC8560CPX667JB integrate?

The MPC8560CPX667JB integrates two independent three-speed (10/100/1000 Mbps) Ethernet controllers, designated TSEC1 and TSEC2. Each supports full-duplex operation, IEEE 802.3z/ab/ac compliance, RMON statistics, 9.6 KB jumbo frames, and multiple PHY interfaces including GMII, MII, RGMII, RTBI, and TBI - as documented in Section 7 of the MPC8560 Hardware Specifications Rev. 4.2.

What is the function of the OCeaN switch fabric in the MPC8560CPX667JB?

OCeaN (On-Chip Ethernet and Networking) is a four-port crossbar packet switch inside the MPC8560CPX667JB that routes traffic between internal blocks - including TSECs, RapidIO, PCI, DDR, and CPM peripherals. It performs priority-based packet reordering, starvation avoidance, and bypass routing to blocked ports, supporting up to 256-byte payloads. This enables deterministic latency for time-critical traffic in wireless baseband applications.

Can the MPC8560CPX667JB operate with DDR-2 memory?

No, the MPC8560CPX667JB supports DDR-1 SDRAM only. Its memory controller is explicitly designed for DDR-1 timing parameters, 2.5 V SSTL2 I/O, and 64-bit data width with four-bank addressing. DDR-2 support was added in subsequent PowerQUICC III processors such as the MPC8548, but the MPC8560CPX667JB's DDR interface lacks DDR-2-specific features like DLL-off mode, additive latency, or 1.8 V signaling.