NXP Semiconductors MPC8560CVT667JC

Overview

MPC8560CVT667JC from NXP (formerly Freescale) is a PowerQUICC III integrated communications processor featuring an e500 core, 667 MHz core frequency, 256 KB L2 cache/SRAM, dual 10/100/1000 Mbps Ethernet controllers (TSEC), DDR-1 SDRAM controller (64-bit, 333 MHz), PCI/PCI-X (64-bit, 133 MHz), and RapidIO (8-bit, 500 MHz data rate). It targets carrier-grade networking infrastructure such as edge routers and wireless baseband units.

For engineers reviewing the MPC8560CVT667JC datasheet, MPC8560CVT667JC pinout, MPC8560CVT667JC application, or MPC8560CVT667JC equivalent, key selection considerations include its 783-pin FC-PBGA package, 1.2 V core supply with 3.3 V/2.5 V I/O domains, support for IEEE 802.3z/ab/ac standards, and compatibility with Power Architecture Book E instruction set for real-time packet processing.

Technical Context

The MPC8560CVT667JC implements a dual-bus architecture: a high-speed Core Complex Bus (CCB) linking the e500 core, L1/L2 caches, and memory controllers, and a peripheral bus managed by the Communications Processor Module (CPM) handling serial protocols (FCC/SCC/MCC), I²C, SPI, and local bus interfaces. Its CPM operates up to 333 MHz and maintains software compatibility with prior PowerQUICC families.

It integrates OCeaN - a four-port crossbar switch fabric enabling priority-based packet reordering and starvation avoidance - alongside a four-channel DMA controller supporting scatter-gather, misaligned transfers, and hardware-enforced coherency. The device supports full ECC on DDR and L2 SRAM/cache, and includes an OpenPIC-compliant programmable interrupt controller with 16 priority levels and 22 internal sources.

Key Specifications

Pinout & Package

The MPC8560CVT667JC is housed in a 35 mm × 35 mm, 783-ball Fine-Pitch Ceramic Ball Grid Array (FC-PBGA) package with 1.0 mm ball pitch and thermal lid. Pin assignments follow Freescale's standardized PowerQUICC III pinout matrix, with dedicated power/ground ball clusters per I/O domain (GVDD, LVDD, OVDD) and differential clock inputs routed to inner rows for signal integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar integrated communications processor applications.

Compared with MPC8560CVT667JC, the MPC8560CVT833JC offers +25% core performance at increased power and thermal cost, while the MPC8548CZQ800B reduces integration breadth (no RapidIO, one TSEC) for lower BOM and layout complexity in entry-level platforms.

Availability

MPC8560CVT667JC is available at Aetrix Electronics and suitable for edge routing, wireless infrastructure, and industrial protocol gateway applications requiring stable component supply and long-term lifecycle support.

Supply support for MPC8560CVT667JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and networking markets, with roots in Freescale's Power Architecture leadership.

The MPC8560CVT667JC belongs to the PowerQUICC III product line, designed specifically for carrier-class communications infrastructure requiring integrated processing, high-speed interconnects, and hardware-accelerated packet handling.

FAQ

What is the maximum DDR-1 data rate supported by the MPC8560CVT667JC?

The MPC8560CVT667JC supports a DDR-1 data rate of up to 333 MHz, delivering a peak theoretical bandwidth of 2.7 GB/s across its 64-bit interface. This is confirmed in Section 4 of the Hardware Specifications document, which specifies "64-bit data interface, up to 333-MHz data rate" and mandates full ECC support for error detection and correction in mission-critical telecom memory subsystems. The MPC8560CVT667JC achieves this using SSTL2-compatible I/O drivers and programmable timing registers for precise setup/hold margining.

Does the MPC8560CVT667JC support IEEE 1588 Precision Time Protocol?

Yes, the MPC8560CVT667JC supports IEEE 1588 PTP through hardware timestamping in its dual TSEC (Three-Speed Ethernet Controller) units. Each TSEC includes dedicated registers for capture and insertion of nanosecond-resolution timestamps on transmit and receive paths, as documented in Chapter 7 of the reference manual. This capability enables sub-microsecond time synchronization in wireless baseband units and industrial gateways - a key requirement for LTE TDD and PROFINET IRT. The MPC8560CVT667JC uses its 125 MHz EC_GTX_CLK125 reference clock as the timebase for PTP operations.

What is the function of the OCeaN switch fabric in the MPC8560CVT667JC?

The OCeaN (On-Chip Ethernet and ATM Network) switch fabric in the MPC8560CVT667JC is a four-port crossbar packet switch that enables non-blocking, priority-based data movement between internal blocks - including TSECs, RapidIO, PCI, and CPM peripherals. It implements starvation avoidance algorithms and packet reordering to ensure deterministic latency for time-sensitive traffic like VoIP and TDM-over-packet. Unlike generic interconnects, OCeaN supports payload sizes up to 256 bytes and integrates directly with the DMA controller for zero-copy transfers. This architecture is essential for the MPC8560CVT667JC's role in carrier-grade packet processing pipelines.

Can the MPC8560CVT667JC operate with a 3.3 V-only I/O configuration?

No, the MPC8560CVT667JC requires multiple I/O voltage domains: GVDD = 2.5 V for DDR signals (SSTL2 compliance), LVDD = 2.5 V or 3.3 V for TSEC depending on PHY interface (RGMII vs. GMII), and OVDD = 3.3 V for PCI, Local Bus, and RapidIO. Section 2.1.3 of the Hardware Specifications explicitly defines these separate rails and warns against exceeding voltage differentials (e.g., LVIN must not exceed LVDD by >0.3 V). Using 3.3 V on GVDD would violate DDR electrical specifications and risk data corruption. The MPC8560CVT667JC's power sequencing - VDD/AVDD first, then GVDD/LVDD/OVDD - further enforces domain separation.

How many independent Ethernet MACs does the MPC8560CVT667JC integrate?

The MPC8560CVT667JC integrates two independent three-speed (10/100/1000 Mbps) Ethernet MACs, implemented as TSEC (Three-Speed Ethernet Controller) units. Both support full-duplex operation, IEEE 802.3z/ab/ac compliance, jumbo frames up to 9.6 KB, and RMON statistics collection. They share no internal resources - each has dedicated FIFOs (2 KB TX/RX), descriptor lists, and MII/GMII/RGMII/TBI interface logic - enabling true parallel 1 Gbps forwarding. This dual-MAC capability is central to the MPC8560CVT667JC's use in redundant network nodes and protocol gateways, as confirmed in Section 7 of the Hardware Specifications.