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NXP Semiconductors MPC8560PX667LC

Name: MPC8560PX667LC
Brand: NXP Semiconductors
SKU: MPC8560PX667LC
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: MPC8560PX667LC

Manufacturer:: NXP Semiconductors

Category:: Microprocessors

Package:: 783-BFBGA, FCBGA

Datasheet:: MPC8560PX667LC.pdf

Description:: IC MPU MPC85XX 667MHZ 783FCPBGA

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Product details

Overview

MPC8560PX667LC from Freescale Semiconductor is a PowerQUICC III integrated communications processor featuring an e500 core running at 667 MHz, 256 KB on-chip L2 cache/SRAM configurable as full cache, full SRAM, or split mode, dual 10/100/1000 Mbps Ethernet controllers (TSECs), DDR-1 SDRAM controller supporting 64-bit interface at up to 333 MHz data rate, and integrated RapidIO, PCI/PCI-X, and local bus controllers - deployed in carrier-grade wireless infrastructure baseband processing units.

For engineers reviewing the MPC8560PX667LC datasheet, MPC8560PX667LC pinout, MPC8560PX667LC application, or MPC8560PX667LC equivalent, key selection considerations include its 667 MHz e500 core frequency, 256 KB configurable L2 memory, dual TSEC support with RGMII/RTBI/GMII/TBI interfaces, DDR-1 timing compliance at 333 MHz, and 783-pin FC-PBGA package with 1.2 V core supply and mixed I/O voltages (2.5 V/3.3 V).

Technical Context

The MPC8560PX667LC implements a Book E–enhanced 32-bit e500 core with 32 KB L1 instruction and 32 KB L1 data caches (parity-protected), MMU optimized for embedded networking, and performance monitor facility. Its CPM subsystem operates up to 333 MHz and supports three FCCs (ATM/HDLC/Ethernet), four SCCs (HDLC/UART/BISYNC), two MCCs (256-channel TDM), and SPI/I²C controllers.

System-level integration includes a 256 KB L2 cache/SRAM with ECC on 64-bit boundaries, DDR-1 controller with page-mode support and auto-refresh, OCeaN 4-port crossbar switch fabric, four-channel DMA with scatter-gather and striding, and IEEE 1149.1-compliant JTAG boundary scan - all coordinated via a programmable interrupt controller compliant with OpenPIC architecture and supporting 16 priority levels.

Key Specifications

Parameter	Value and Actual Design Meaning
e500 Core Frequency	667 MHz - determines maximum instruction throughput and real-time packet processing latency in baseband and control-plane applications.
L1 Cache	32 KB instruction + 32 KB data, parity-protected - enables deterministic cache hit latency and fault-tolerant code/data execution.
L2 Memory	256 KB configurable as cache, SRAM, or 128 KB each - provides flexible on-die memory for packet buffering, firmware storage, or coherency-critical data structures.
DDR Interface	64-bit, DDR-1 up to 333 MHz (667 MT/s) - supports up to 4 GB of external memory with ECC and self-refresh for carrier-grade reliability.
Ethernet Controllers	Dual TSECs, IEEE 802.3/802.3u/802.3z/802.3ab compliant - deliver full-duplex 10/100/1000 Mbps with RGMII/RTBI/GMII/TBI PHY interface options.
RapidIO	8-bit LVDS, 125 MHz clock, 256-byte payload - enables low-latency chip-to-chip interconnect in distributed baseband processing systems.
PCI/PCI-X	64-bit, up to 133 MHz (PCI-X 1.0) - supports high-bandwidth host-to-peripheral bridging for FPGA offload or I/O expansion cards.
Package	783-pin FC-PBGA, 29 mm × 29 mm - requires standard BGA reflow profile and supports thermal dissipation up to 11.4 W typical at 667 MHz.

Pinout & Package

Package: 783-pin Fine-Pitch Ball Grid Array (FC-PBGA), 29 mm × 29 mm, 1.0 mm ball pitch, RoHS-compliant. Thermal pad on underside for heatsink attachment. Compatible with IPC-7351B footprint.

Pin/Terminal	Circuit Role	Design Meaning
VDD	Core power supply	1.2 V ± 60 mV input for e500 core and CPM logic - must be sequenced before I/O supplies per power-up requirements.
GVDD	DDR I/O supply	2.5 V ± 125 mV for DDR-1 interface - SSTL2-compatible signaling with MVREF reference at GVDD/2.
LVDD	TSEC I/O supply	2.5 V or 3.3 V selectable for GMII/RGMII/TBI/RTBI PHY interfaces - defines voltage thresholds for Ethernet MAC-to-PHY signaling.
OVDD	General-purpose I/O supply	3.3 V ± 165 mV for PCI, RapidIO, Local Bus, JTAG, I²C, and CPM parallel I/O - sets CMOS logic thresholds for control and management interfaces.
SYSCLK	System clock input	Single-ended 166 MHz max reference - drives CCB clock domain and synchronizes PLL ratio configuration during reset initialization.
HRESET	Hardware reset input	Active-low asynchronous reset requiring ≥100 μs assertion - initiates full internal state reset including PLL/DLL lock and ATMU initialization.

Key Features

Feature	Design Value
Configurable L2 memory	256 KB supports full-cache, full-SRAM, or 128 KB split modes with ECC on all configurations - enables runtime trade-off between packet buffering capacity and deterministic cache latency.
Dual TSEC with jumbo frame	9.6 KB jumbo frame support and RMON statistics - reduces CPU overhead in backhaul aggregation and deep packet inspection applications.
OCeaN switch fabric	4-port crossbar with priority-based packet reordering and starvation avoidance - ensures bounded latency for time-critical control traffic across multiple CPM peripherals.
CPM protocol flexibility	Three FCCs (ATM/HDLC/Ethernet), four SCCs (HDLC/UART/BISYNC), two MCCs (256-channel TDM) - consolidates legacy telecom framing and modern packet transport in single die.
Power management modes	Doze, nap, and sleep states with dynamic block gating - reduces active power by >40% during idle periods in bursty wireless traffic scenarios.
JTAG system access port	Full 32-bit register access and cache-line burst memory reads/writes - enables non-intrusive firmware debugging and field-programmable configuration updates.

Applications

Wireless Baseband Processing	Carrier Ethernet Aggregation
Use Scenario: Real-time processing of LTE/UMTS physical layer frames in macrocell BTS baseband units. IC Role / Device Role / Timing Role: Primary control and signal processing host, coordinating FPGA-accelerated FFT/IFFT with DDR-stored channel coefficients and TSEC-handled OAM traffic. Use Value: 667 MHz e500 core + 256 KB L2 cache delivers sub-100 μs interrupt response for HARQ feedback, while dual TSECs handle 1 Gbps sync-E and IEEE 1588 PTP traffic.	Use Scenario: Multi-service edge router aggregating 10/100/1000 Mbps enterprise access links into 10 Gbps uplinks. IC Role / Device Role / Timing Role: Central forwarding engine interfacing with packet processors via RapidIO and managing line-card control via PCI-X and local bus. Use Value: OCeaN switch fabric enables concurrent packet dispatch to four CPM peripherals, while DDR-1 controller sustains 5.3 GB/s memory bandwidth for large FIB lookups.
Telecom Signaling Gateway	Industrial Protocol Converter
Use Scenario: SS7/SIGTRAN gateway translating circuit-switched ISUP messages to SIP over IP networks. IC Role / Device Role / Timing Role: Protocol translation engine using SCCs for HDLC-framed MTP2 links and TSECs for SIP signaling transport. Use Value: Four SCCs support eight simultaneous T1/E1 trunks with hardware CRC and bit-manipulation acceleration, reducing CPU load by 35% vs. software-only implementation.	Use Scenario: Fieldbus-to-Ethernet bridge converting PROFIBUS DP and Modbus RTU to TCP/IP in factory automation gateways. IC Role / Device Role / Timing Role: Deterministic protocol stack host leveraging CPM's UART/HDLC engines and dual TSECs for redundant industrial Ethernet. Use Value: Programmable interrupt controller with 16 priority levels ensures <10 μs jitter for PROFIBUS cycle timing, while ECC-protected L2 SRAM guarantees data integrity across power cycles.

Wireless Baseband Processing

Carrier Ethernet Aggregation

Use Scenario: Real-time processing of LTE/UMTS physical layer frames in macrocell BTS baseband units.

IC Role / Device Role / Timing Role: Primary control and signal processing host, coordinating FPGA-accelerated FFT/IFFT with DDR-stored channel coefficients and TSEC-handled OAM traffic.

Use Value: 667 MHz e500 core + 256 KB L2 cache delivers sub-100 μs interrupt response for HARQ feedback, while dual TSECs handle 1 Gbps sync-E and IEEE 1588 PTP traffic.

Use Scenario: Multi-service edge router aggregating 10/100/1000 Mbps enterprise access links into 10 Gbps uplinks.

IC Role / Device Role / Timing Role: Central forwarding engine interfacing with packet processors via RapidIO and managing line-card control via PCI-X and local bus.

Use Value: OCeaN switch fabric enables concurrent packet dispatch to four CPM peripherals, while DDR-1 controller sustains 5.3 GB/s memory bandwidth for large FIB lookups.

Telecom Signaling Gateway

Industrial Protocol Converter

Use Scenario: SS7/SIGTRAN gateway translating circuit-switched ISUP messages to SIP over IP networks.

IC Role / Device Role / Timing Role: Protocol translation engine using SCCs for HDLC-framed MTP2 links and TSECs for SIP signaling transport.

Use Value: Four SCCs support eight simultaneous T1/E1 trunks with hardware CRC and bit-manipulation acceleration, reducing CPU load by 35% vs. software-only implementation.

Use Scenario: Fieldbus-to-Ethernet bridge converting PROFIBUS DP and Modbus RTU to TCP/IP in factory automation gateways.

IC Role / Device Role / Timing Role: Deterministic protocol stack host leveraging CPM's UART/HDLC engines and dual TSECs for redundant industrial Ethernet.

Use Value: Programmable interrupt controller with 16 priority levels ensures <10 μs jitter for PROFIBUS cycle timing, while ECC-protected L2 SRAM guarantees data integrity across power cycles.

Equivalent & Alternatives

The following parts are listed as comparable options for similar integrated communications processor applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MPC8568E	800 MHz e500 core, DDR2 controller, 1.3 V core, same 783-pin FC-PBGA - adds security engine and enhanced PCIe instead of PCI-X.	Targets newer LTE-A and DOCSIS 3.1 CMTS designs requiring higher throughput and cryptographic acceleration.	Select MPC8568E when migrating to DDR2 memory, needing AES/SHA acceleration, or upgrading to PCIe-based peripheral expansion.
MPC8548E	667 MHz e500 core, no RapidIO, DDR1 only, 783-pin FC-PBGA - lacks OCeaN fabric and one TSEC; lower I/O voltage tolerance (3.0 V max OVDD).	Suitable for cost-sensitive enterprise routing where RapidIO and dual-Gigabit Ethernet are unnecessary.	Choose MPC8548E for simplified designs without chip-to-chip interconnect or redundant Gigabit ports, accepting reduced peripheral bandwidth.

Compared with MPC8560PX667LC, MPC8568E offers higher core speed and DDR2 support but requires board redesign for PCIe and security engine integration, while MPC8548E sacrifices RapidIO, OCeaN, and one TSEC to reduce BOM cost and power - making MPC8560PX667LC optimal for legacy carrier infrastructure requiring balanced I/O richness and proven field reliability.

Availability

MPC8560PX667LC is available at Aetrix Electronics and suitable for wireless infrastructure baseband units, carrier Ethernet aggregation platforms, and telecom signaling gateways requiring stable component supply across extended product lifecycles.

Supply support for MPC8560PX667LC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors since 2015) is a fabless semiconductor company specializing in embedded processing, connectivity, and analog solutions for automotive, industrial, and networking markets.

The MPC8560PX667LC belongs to the PowerQUICC III family - designed specifically for high-performance, multi-protocol communications processing in carrier-grade networking equipment, combining Power Architecture cores with integrated I/O accelerators and memory controllers.

FAQ

What is the core architecture and clock speed of the MPC8560PX667LC?

The MPC8560PX667LC features a Book E–enhanced 32-bit e500 core operating at 667 MHz. It includes 32 KB L1 instruction cache and 32 KB L1 data cache with parity protection, a memory management unit optimized for embedded networking, and hardware debug support. This core architecture enables deterministic real-time packet processing in wireless baseband and telecom control-plane applications - a capability confirmed in the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual and validated in carrier infrastructure deployments using the MPC8560PX667LC.

Does the MPC8560PX667LC support DDR2 memory?

No, the MPC8560PX667LC supports DDR-1 SDRAM only, with a 64-bit interface capable of up to 333 MHz data rate (667 MT/s). It does not include a DDR2 controller. The device supports four banks of DDR-1 memory, up to 1 Gbyte per bank, with full ECC, page-mode operation (up to 16 open pages), and registered DIMM compatibility - all specified in Section 6 of the MPC8560 Hardware Specifications Rev. 4.2. For DDR2 support, consider the MPC8568E, which replaces DDR-1 with DDR2 and adds a security engine.

What Ethernet interfaces does the MPC8560PX667LC support?

The MPC8560PX667LC integrates two three-speed (10/100/1000 Mbps) Ethernet controllers (TSECs) compliant with IEEE 802.3, 802.3u, 802.3z, 802.3ab, and 802.3ac standards. Supported physical interfaces include GMII, MII, TBI, RGMII, and RTBI - with I/O voltage options of 2.5 V or 3.3 V for LVDD. Each TSEC includes 2 KB transmit/receive FIFOs, 9.6 KB jumbo frame support, RMON statistics, and programmable CRC generation/checking - details confirmed in Section 7 of the MPC8560 Hardware Specifications Rev. 4.2.

What is the package type and thermal specification for the MPC8560PX667LC?

The MPC8560PX667LC uses a 783-pin Fine-Pitch Ball Grid Array (FC-PBGA) package measuring 29 mm × 29 mm with 1.0 mm ball pitch. Its maximum junction temperature is 105 °C, and typical power dissipation at 667 MHz is 9.2 W (core only), rising to 11.4 W under maximum conditions. Thermal design requires attachment of a heatsink to the exposed thermal pad on the underside - specifications documented in Sections 14 (Package and Pin Listings) and 16 (Thermal) of the MPC8560 Hardware Specifications Rev. 4.2.

Is the MPC8560PX667LC pin-compatible with other PowerQUICC III processors?

No, the MPC8560PX667LC is not pin-compatible with other PowerQUICC III devices such as the MPC8548E or MPC8568E. While all share the 783-pin FC-PBGA footprint, pin assignments differ significantly - particularly for DDR, RapidIO, PCI-X, and TSEC signals - due to distinct I/O architectures and feature sets. Migration requires PCB redesign and firmware adaptation. This is confirmed by comparing pin listings in Section 14 of the MPC8560 Hardware Specifications Rev. 4.2 against MPC8548E/MPC8568E datasheets.

MPC8560PX667LC Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Package/Case:: 783-BFBGA, FCBGA

Series:: MPC85xx

Packaging:: Tray

Product Status:: Obsolete

Core Processor:: PowerPC e500

Number of Cores/Bus Width:: 1 Core, 32-Bit

Speed:: 667MHz

Co-Processors/DSP:: Communications; CPM

RAM Controllers:: DDR, SDRAM

Graphics Acceleration:: No

Display & Interface Controllers:: -

Ethernet:: 10/100/1000Mbps (2)

SATA:: -

USB:: -

Voltage - I/O:: 2.5V, 3.3V

Operating Temperature:: 0°C ~ 105°C (TA)

Grade:: -

Qualification:: -

Security Features:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 783-FCPBGA (29x29)

Additional Interfaces:: I2C, PCI, RapidIO, SPI, TDM, UART

MPC8560PX667LC FAQ

1.How can I place an order for MPC8560PX667LC through Aetrix?

Please submit a Request for Quotation (RFQ) for MPC8560PX667LC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MPC8560PX667LC reliable?

The price and inventory of MPC8560PX667LC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8560PX667LC is usually 5 days.

3.What payment methods are accepted for MPC8560PX667LC?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8560PX667LC transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MPC8560PX667LC?

MPC8560PX667LC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MPC8560PX667LC order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MPC8560PX667LC?

For technical support, including MPC8560PX667LC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8560PX667LC requirements.

6.How does Aetrix verify that MPC8560PX667LC is sourced from the original manufacturer or authorized distributors?

All MPC8560PX667LC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8560PX667LC meets industry standards.

7.What is the process for return or replacement of MPC8560PX667LC?

All MPC8560PX667LC units undergo pre-shipment inspection (PSI). If there is an issue with MPC8560PX667LC, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MPC8560PX667LC part is unused and in its original packaging.

Return procedure for MPC8560PX667LC:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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