NXP Semiconductors MPC8560VT667LC
- Part No.:
- MPC8560VT667LC
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- -
- Datasheet:
-
MPC8560VT667LC.pdf
- Description:
- RISC MICROPROCESSOR, 32-BIT, 667
- Quantity:
- Payment:

- Shipping:

Inventory:3,686
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MPC8560VT667LC from Freescale Semiconductor is a PowerQUICC III integrated communications processor featuring an e500 core, 256 KB L2 cache/SRAM, dual 10/100/1000 Mbps Ethernet controllers (TSECs), DDR-1 SDRAM controller (64-bit, up to 333 MHz), PCI/PCI-X (64-bit, up to 133 MHz), and 8-bit RapidIO interface - deployed in carrier-grade networking infrastructure, wireless baseband units, and telecom edge routers.
For engineers reviewing the MPC8560VT667LC datasheet, MPC8560VT667LC pinout, MPC8560VT667LC application, or MPC8560VT667LC equivalent, key selection criteria include its 667 MHz e500 core frequency, 1.2 V core supply, 783-pin FC-PBGA package, DDR-1 memory controller timing compliance, and dual TSEC support for IEEE 802.3z/ab/3ac Gigabit Ethernet PHY interfacing.
Technical Context
The MPC8560VT667LC implements a Book E–enhanced 32-bit e500 core with 32 KB L1 instruction and 32 KB L1 data caches (parity-protected), MMU optimized for embedded real-time OS environments, and performance monitor facility supporting eight 32-bit event counters. Its CPM subsystem operates at up to 333 MHz and handles serial protocols including HDLC, ATM via UTOPIA, and ISDN PRI through eight TDM interfaces.
System-level integration includes an OCeaN four-port crossbar switch for packet reordering and starvation avoidance, a four-channel DMA controller with scatter-gather and misaligned transfer support, and dual TSECs with RMON statistics, 9.6-Kbyte jumbo frame capability, and configurable CRC generation/checking - all coordinated via a coherency-enabled Core Complex Bus (CCB) running at 333 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| e500 Core Frequency | 667 MHz - determines maximum instruction throughput and real-time deterministic latency for control-plane processing. |
| L1 Cache | 32 KB instruction + 32 KB data, parity-protected - enables high hit rate for firmware and protocol stack execution with error detection. |
| L2 Memory | 256 KB configurable as cache, SRAM, or split mode - supports low-latency packet buffering or shared memory for multi-core-like communication between CPM and e500. |
| DDR Interface | 64-bit, DDR-1 SDRAM, up to 333 MHz data rate - delivers up to 5.3 GB/s peak bandwidth for packet buffer and table storage. |
| TSEC Count | 2 × 10/100/1000 Mbps controllers - provides redundant or dual-link Gigabit Ethernet connectivity compliant with IEEE 802.3z/ab/3ac. |
| PCI/PCI-X Support | 64-bit, up to 133 MHz (PCI-X 1.0) - enables high-bandwidth attachment of network accelerators, crypto modules, or legacy I/O cards. |
| RapidIO Interface | 8-bit, source-synchronous DDR, LVDS signaling - supports chip-to-chip interconnect with 16 Gb/s aggregate bandwidth for distributed processing nodes. |
Pinout & Package
Package: 783-ball Fine-Pitch Ceramic Pin Grid Array (FC-PBGA), 27 mm × 27 mm, 1.0 mm ball pitch, RoHS-compliant. Thermal pad on underside requires solder paste stencil design per Freescale AN2912.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (Core) | Core power supply | 1.2 V ± 60 mV nominal; must be sequenced before I/O supplies to prevent latch-up during power-up. |
| GVDD | DDR I/O supply | 2.5 V ± 125 mV; powers SSTL2-compatible DDR interface; referenced by MVREF = GVDD/2. |
| LVDD | TSEC I/O supply | Configurable 2.5 V or 3.3 V; sets voltage level for GMII/RGMII/TBI/RTBI physical layer interfacing. |
| OVDD | General-purpose I/O supply | 3.3 V ± 165 mV; powers PCI, Local Bus, CPM, JTAG, I2C, and system control signals. |
| HRESET | Hardware reset input | Active-low asynchronous reset requiring ≥100 μs assertion; initiates full internal state initialization and PLL lock sequence. |
| SYSCLK | Primary system clock input | 166 MHz max differential or single-ended reference; drives CCB, e500 core, and peripheral clocks via programmable PLL ratios. |
Key Features
| Feature | Design Value |
|---|---|
| OCeaN Switch Fabric | Four-port crossbar enabling non-blocking packet routing between TSECs, RapidIO, PCI, and CPM - eliminates bus contention in multi-protocol traffic forwarding. |
| ATMU Configuration | Eight local access windows plus inbound/outbound translation for PCI and RapidIO - allows flexible memory-mapped I/O and secure address space partitioning across heterogeneous masters. |
| CPM Serial Protocol Support | Three FCCs (ATM/HDLC), two MCCs (256-channel HDLC/TDM), four SCCs (UART/SDLC/BISYNC) - consolidates legacy telecom framing and control into single silicon. |
| Power Management Modes | Doze, nap, and sleep states with dynamic block gating - reduces active power by >40% during idle periods without compromising wake latency for real-time packet arrival. |
| JTAG System Access Port | Full 32-bit register and cache-line memory access via boundary scan - enables in-system debug, firmware patching, and post-silicon validation without external probes. |
Applications
| Wireless Base Station Controller | Carrier Ethernet Aggregation Router |
|---|---|
Use Scenario: Centralized control unit managing multiple remote radio heads (RRHs) via CPRI-over-Ethernet or TDM backhaul links. IC Role / Device Role / Timing Role: MPC8560VT667LC serves as the control-plane processor handling OAM&P, synchronization distribution (IEEE 1588 PTP), and Layer 2 switching via dual TSECs and OCeaN fabric. Use Value: 667 MHz e500 core and 256 KB L2 SRAM enable deterministic response to fronthaul timing alarms within <50 μs, while dual TSECs support redundant 1 Gbps backhaul paths. | Use Scenario: Multi-service edge router aggregating DSL, GPON, and LTE subscriber traffic onto metro Ethernet rings. IC Role / Device Role / Timing Role: MPC8560VT667LC acts as the integrated forwarding engine, executing QoS policy, VLAN translation, and MPLS label imposition using CPM-based HDLC framing and TSEC-based packet classification. Use Value: Dual TSECs with RMON and jumbo frame support deliver line-rate 1 Gbps throughput per port; DDR-1 controller sustains 10K+ concurrent subscriber sessions in packet buffer RAM. |
| Telecom Signaling Gateway | Industrial Protocol Converter |
Use Scenario: SS7/IP gateway translating legacy circuit-switched signaling (MTP2/MTP3) to SIP/ISUP over IP networks. IC Role / Device Role / Timing Role: MPC8560VT667LC functions as the protocol translation engine, leveraging FCCs for SS7 MTP2 framing and TSECs for SIP transport, coordinated via OCeaN fabric. Use Value: Three FCCs support simultaneous SS7 A-links and B-links; ECC-protected L2 cache ensures bit-error-free signaling message integrity across 24/7 operation. | Use Scenario: Field device gateway bridging Modbus RTU (RS-485) and PROFINET (100 Mbps) in factory automation systems. IC Role / Device Role / Timing Role: MPC8560VT667LC operates as real-time protocol translator, using SCCs for Modbus UART/HDLC and TSEC for PROFINET MAC-layer handling. Use Value: Four SCCs provide independent serial channel isolation; programmable interrupt controller enables sub-100 μs response to PROFIdrive motion control events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8548CZQ800B | 800 MHz e500 core, same 783-pin FC-PBGA, but lacks RapidIO; adds SATA and USB 2.0. | Better suited for storage-attached gateways; not viable for RapidIO-based distributed baseband architectures. | Select when PCIe/SATA host interface required over chip-to-chip RapidIO interconnect. |
| P2020NSN2KFC | Power Architecture e500v2 core at 1.2 GHz, 2× DDR3, 2× 10-GbE XAUI, but no CPM or TDM support. | Targets next-gen data center edge; incompatible with legacy TDM/HDLC/UTOPIA telecom protocols. | Choose for high-throughput packet forwarding where legacy serial protocol offload is handled externally. |
Compared with MPC8560VT667LC, MPC8548CZQ800B trades RapidIO for SATA/USB and higher clock speed, while P2020NSN2KFC abandons CPM entirely for modern high-speed SerDes - making MPC8560VT667LC uniquely suitable for brownfield telecom upgrades requiring hardware-accelerated TDM and ATM framing.
Availability
MPC8560VT667LC is available at Aetrix Electronics and suitable for carrier-grade networking infrastructure, wireless baseband units, and telecom edge routers requiring stable component supply across extended product lifecycles.
Supply support for MPC8560VT667LC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Freescale Semiconductor (now part of NXP Semiconductors since 2015) is a fabless semiconductor company specializing in embedded processing, analog, and connectivity solutions for automotive, industrial, and networking markets.
The MPC8560VT667LC belongs to the PowerQUICC III family - designed specifically for integrated control- and data-plane processing in communications infrastructure where deterministic latency, multi-protocol serial I/O, and DDR-1 memory bandwidth are critical.
FAQ
What is the maximum DDR-1 data rate supported by the MPC8560VT667LC?
The MPC8560VT667LC supports a maximum DDR-1 data rate of 333 MHz, delivering up to 5.3 GB/s peak bandwidth on its 64-bit interface. This is confirmed in Section 4 of the MPC8560 Hardware Specifications (Rev. 4.2), which specifies programmable timing for DDR-1 SDRAM with four banks, each supporting up to 1 Gbyte. The interface is 2.5-V SSTL2 compatible and includes full ECC support on 64-bit boundaries.
Does the MPC8560VT667LC include hardware support for IEEE 1588 Precision Time Protocol?
The MPC8560VT667LC does not include dedicated IEEE 1588 hardware timestamping logic. While its dual TSECs support standard Ethernet MAC functionality and can be software-configured for PTP message handling, precise sub-microsecond timestamping requires external PHYs with 1588 support or FPGA-based offload - as confirmed by absence of "PTP", "timestamp", or "1588" in the MPC8560EC Rev. 4.2 specification document sections covering TSEC, CPM, and system timers.
What is the thermal design power (TDP) of the MPC8560VT667LC at 667 MHz operation?
At 667 MHz core frequency and 333 MHz CCB frequency, the MPC8560VT667LC has a typical VDD power dissipation of 6.4 W and a maximum of 9.2 W, excluding I/O supply power (GVDD, LVDD, OVDD) and AVDD. Total system power - including DDR, PCI, and TSEC I/O - reaches approximately 10.5 W under full load, as derived from Tables 4–6 in the Hardware Specifications (Rev. 4.2).
Can the MPC8560VT667LC boot directly from SPI flash?
No, the MPC8560VT667LC does not support direct boot from SPI flash. Its boot sequencer is explicitly designed to load configuration data from serial ROM via the I2C interface only, as stated in Section 1.1 (Boot Sequencer) of the Hardware Specifications. SPI interface support is limited to peripheral master/slave operation via the dedicated SPI controller - not boot ROM access.
Is the MPC8560VT667LC pin-compatible with other MPC8560 speed grades like MPC8560VT800C?
Yes, the MPC8560VT667LC is pin-compatible with other MPC8560 variants in the 783-ball FC-PBGA package, including MPC8560VT800C and MPC8560VT1000C. All share identical mechanical footprint, ball map, and signal assignment per Section 14 ("Package and Pin Listings") of the Hardware Specifications. Differences are limited to speed grade, thermal specifications, and internal PLL configuration - requiring no PCB redesign for migration.
MPC8560VT667LC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- -
- Series:
- *
- Packaging:
- Bulk
- Product Status:
- Active
- Core Processor:
- -
- Number of Cores/Bus Width:
- -
- Speed:
- -
- Co-Processors/DSP:
- -
- RAM Controllers:
- -
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- -
- SATA:
- -
- USB:
- -
- Voltage - I/O:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Additional Interfaces:
- -
MPC8560VT667LC FAQ
1.How can I place an order for MPC8560VT667LC through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8560VT667LC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8560VT667LC reliable?
The price and inventory of MPC8560VT667LC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8560VT667LC is usually 5 days.
3.What payment methods are accepted for MPC8560VT667LC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8560VT667LC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8560VT667LC?
MPC8560VT667LC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8560VT667LC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8560VT667LC?
For technical support, including MPC8560VT667LC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8560VT667LC requirements.
6.How does Aetrix verify that MPC8560VT667LC is sourced from the original manufacturer or authorized distributors?
All MPC8560VT667LC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8560VT667LC meets industry standards.
7.What is the process for return or replacement of MPC8560VT667LC?
All MPC8560VT667LC units undergo pre-shipment inspection (PSI). If there is an issue with MPC8560VT667LC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8560VT667LC part is unused and in its original packaging.
Return procedure for MPC8560VT667LC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MPC8560VT667LC Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

