NXP Semiconductors MPC8572EVJARLE

Overview

MPC8572EVJARLE from NXP is a dual-core Power Architecture® e500-based integrated communications processor with two 32-bit Book E-enhanced cores, 1 Mbyte shared L2 cache/SRAM with full ECC, dual 64-bit DDR2/DDR3 memory controllers (up to 32 GB total), four enhanced three-speed Ethernet controllers (eTSECs), integrated security engine (SEC) supporting AES, SHA-2, RSA up to 4096 bits, and Serial RapidIO® 1.2 interface. It targets high-throughput network infrastructure applications including enterprise routers, carrier-grade gateways, and secure wireless baseband systems.

For engineers reviewing the MPC8572EVJARLE datasheet, MPC8572EVJARLE pinout, MPC8572EVJARLE application, or MPC8572EVJARLE equivalent, key selection considerations include its dual-e500 core timing behavior, DDR2/DDR3 voltage tolerance (1.5 V / 1.8 V), 1023-pin FC-PBGA package thermal profile, SEC crypto-channel concurrency, and eTSEC TCP/IP offload capabilities in real-world packet processing workloads.

Technical Context

The MPC8572EVJARLE implements two identical e500v2 cores with separate 32-Kbyte L1 instruction and data caches (parity-protected), SPE and double-precision floating-point APUs, and a unified 36-bit real address space managed by an embedded MMU supporting 4-Kbyte to 4-Gbyte page sizes. Its coherency is maintained via the e500 Coherency Module (ECM).

Memory subsystem includes dual independent 64-bit DDR2/DDR3 controllers with full ECC, on-die termination, registered DIMM support, and auto-refresh; plus a flexible 1-Mbyte L2 cache/SRAM with eight-way set-associative organization, per-way allocation, and stashing capability for external masters. The integrated OCeaN switch fabric enables low-latency interconnect between internal units.

Key Specifications

Pinout & Package

Package: 1023-pin FC-PBGA (35 mm × 35 mm, 1.0 mm ball pitch). Pinout reflects multiplexed high-speed I/O configuration supporting selectable interface combinations: single x8/x4/x2/x1 PCI Express; dual x4/x2/x1 PCI Express; or single x4/x2/x1 PCI Express + dual x2/x1 PCI Express; or single 1x/4x Serial RapidIO + single x4/x2/x1 PCI Express.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core communications processor applications.

Compared with MPC8572EVJARLE, MPC8572EVRARLE offers identical functionality with lead-free packaging for regulatory compliance, while MPC8548CVRALF trades dual-core throughput, advanced security, and DDR3 support for lower cost and power in less demanding control-plane roles.

Availability

MPC8572EVJARLE is available at Aetrix Electronics and suitable for enterprise routing, carrier gateway, and secure industrial firewall applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for production programs.

Supply support for MPC8572EVJARLE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and networking markets.

The MPC8572EVJARLE belongs to NXP's PowerQUICC III family-designed specifically for high-performance, secure packet processing in carrier and enterprise networking equipment, integrating communications peripherals, security acceleration, and memory subsystems on a single die.

FAQ

What is the maximum DDR3 data rate supported by the MPC8572EVJARLE?

The MPC8572EVJARLE supports DDR3 SDRAM at 1.5 V with data rates up to 800 MT/s (DDR3-1600), enabled by its dual 64-bit DDR3 controllers featuring on-die termination, programmable timing, and auto-refresh. This is confirmed in Section 6 of the MPC8572EEC Rev. 7 specification, which defines DDR3 operation at 1.5 V ± 75 mV and supports configurations up to 4 Gbytes per bank across four banks per controller. The MPC8572EVJARLE achieves this using differential DQS signaling referenced to MVREFn = GVDD/2 ± 1%.

Does the MPC8572EVJARLE support PCIe Gen2 or higher?

No, the MPC8572EVJARLE implements PCI Express 1.0a compliant controllers only, supporting link widths of x1, x2, x4, or x8 at 2.5 GT/s per lane. It does not support PCIe Gen2 (5.0 GT/s) or later revisions. This limitation is explicitly stated in Section 16 of the MPC8572EEC Rev. 7 document, which specifies "PCI Express 1.0a compatible" operation and lists maximum payload size (256 bytes) and virtual channel support (VC0 only) consistent with Gen1 architecture.

Can the MPC8572EVJARLE operate with DDR2 and DDR3 memory simultaneously?

No, the MPC8572EVJARLE cannot operate DDR2 and DDR3 memory simultaneously on the same controller. Each of its two DDR controllers can be independently configured for either DDR2 (1.8 V) or DDR3 (1.5 V), but not both concurrently. Section 6.1 of the MPC8572EEC Rev. 7 states: "The DDR2/DDR3 SDRAM controller supports DDR2 and DDR3 SDRAM," and Table 2 confirms separate GVDD voltage requirements-1.8 V ± 90 mV for DDR2 and 1.5 V ± 75 mV for DDR3-requiring distinct power domains.

What is the role of the OCeaN switch fabric in the MPC8572EVJARLE architecture?

The OCeaN (On-Chip Ethernet and Networking) switch fabric in the MPC8572EVJARLE is a full-crossbar interconnect that routes data between internal masters (eTSECs, DMA, SEC, L2 cache) and slaves (memory controllers, I/O peripherals) without CPU involvement. As described in Section 1.1 and Figure 1 of MPC8572EEC Rev. 7, it enables zero-copy transfers, prioritizes traffic to avoid starvation, and reorders packets to bypass blocked paths-critical for sustaining line-rate throughput across multiple eTSECs and crypto channels in the MPC8572EVJARLE.

Is the MPC8572EVJARLE pin-compatible with other PowerQUICC III processors like the MPC8548?

No, the MPC8572EVJARLE is not pin-compatible with the MPC8548 or other PowerQUICC III variants. It uses a 1023-pin FC-PBGA package, whereas the MPC8548 uses a 783-pin or 957-pin PBGA. Pin assignments differ significantly due to added peripherals-including four eTSECs (vs. one in MPC8548), dual RapidIO lanes, and expanded DDR3 I/O-making PCB redesign mandatory. This is confirmed by comparing Package Description sections (Section 18) across MPC8572EEC Rev. 7 and MPC8548EC Rev. 5 documents.