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NXP Semiconductors MPC8572EVTARLD
- Part No.:
- MPC8572EVTARLD
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 1023-BFBGA, FCBGA
- Datasheet:
-
MPC8572EVTARLD.pdf
- Description:
- IC MPU MPC85XX 1.067GHZ 1023BGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,358
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Product details
Overview
MPC8572EVTARLD from NXP is a dual-core Power Architecture® e500-based integrated communications processor targeting high-performance networking and telecom infrastructure applications. It integrates two 32-bit e500v2 cores, 1 Mbyte shared L2 cache/SRAM with full ECC, dual 64-bit DDR2/DDR3 memory controllers (up to 16 GB per controller), four eTSEC Ethernet controllers (10/100/1000 Mbps), integrated security engine (SEC) with AES/SHA/RSA acceleration, and Serial RapidIO® 1.2 interface. It is used in carrier-grade routers, media gateways, and secure edge appliances.
For engineers reviewing the MPC8572EVTARLD datasheet, MPC8572EVTARLD pinout, MPC8572EVTARLD application, or MPC8572EVTARLD equivalent, key selection criteria include dual-e500 core performance at up to 1.5 GHz, hardware-accelerated IPSec/SSL/TLS offload, DDR3-1333 support with ECC, 1023-pin FC-PBGA package compatibility, and deterministic low-latency packet processing via OCeaN switch fabric and Pattern Matching Engine.
Technical Context
The MPC8572EVTARLD implements two identical e500v2 cores with 32-Kbyte L1 instruction and data caches (parity-protected), SPE and double-precision floating-point APUs, and 36-bit real addressing with MMU supporting 4-Kbyte to 4-Gbyte page sizes. Its coherency is managed by the e500 Coherency Module (ECM), and address translation uses twelve local ATMU windows plus inbound/outbound mappings for PCI Express and Serial RapidIO.
Hardware acceleration includes a dedicated Security Engine (SEC) with four crypto-channels, PKEU (RSA up to 4096 bits), AESU (128/192/256-bit keys, GCM/CCM modes), MDEU (SHA-1/256/384/512, HMAC), and RNG; plus a Pattern Matching Engine supporting 16,000 regex patterns and DEFLATE decompression, tightly coupled with the OCeaN crossbar switch for zero-copy packet steering.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Dual e500v2 32-bit Power Architecture cores with SPE, scalar & double-precision FP APUs |
| L1 Cache | 32-Kbyte instruction + 32-Kbyte data per core, parity-protected, line- or full-lockable |
| L2 Memory | 1-Mbyte unified cache/SRAM, 8-way set-associative, full ECC on 64-bit boundary, configurable per core |
| Memory Interface | Dual 64-bit DDR2/DDR3 controllers; supports 4 banks × 4 GB = 16 GB per controller; 1.8-V SSTL_1.8 / 1.5-V DDR3 I/O |
| Ethernet | Four eTSECs: IEEE 802.3-compliant 10/100/1000 Mbps with TCP/IP offload (checksum, VLAN, MPLS, IPsec) |
| High-Speed I/O | Serial RapidIO 1.2 (1x/4x, 2.5 Gbps/lane), three PCI Express 1.0a controllers (x1/x2/x4/x8), dual I²C, DUART |
| Security Engine | SEC with AES-128/192/256, SHA-1/256/384/512, RSA-4096, ECC-1023, RNG, CRC-32/CRC-32C |
| Package | 1023-pin Fine-Pitch Ceramic Ball Grid Array (FC-PBGA), 35 mm × 35 mm, 1.0 mm pitch |
Pinout & Package
Package: 1023-pin FC-PBGA (35 mm × 35 mm, 1.0 mm ball pitch), RoHS-compliant, thermal lid-equipped for industrial temperature operation (0°C to 105°C junction).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, AVDD, SVDD, XVDD | Core & SerDes power supplies | 1.1 V ± 55 mV nominal; strict sequencing required (VDD before GVDD) to prevent DDR initialization failure |
| GVDD | DDR2/DDR3 I/O supply | 1.8 V ± 90 mV (DDR2) or 1.5 V ± 75 mV (DDR3); referenced by MVREFn = GVDD/2 ± 1% |
| LVDD / TVDD | eTSEC I/O supply | 3.3 V or 2.5 V; supports GMII/MII/RGMII/SGMII; overshoot/undershoot limited to ±0.3 V |
| OVDD | DUART/I²C/JTAG supply | 3.3 V ± 165 mV; drives CMOS-compatible logic; I²C pull-up requires external 150 Ω drive strength |
| BVDD | Local bus & GPIO supply | 3.3 V / 2.5 V / 1.8 V; programmable drive strength (25–125 Ω) via PORIMPSCR register |
| RESET_IN | Asynchronous reset input | Active-low; initiates full chip reset including L2 cache flush, MMU disable, and boot sequencer activation |
| BOOT_CFG[0:3] | Boot configuration strap pins | Sampled at reset; select boot source (I²C serial ROM, NOR/NAND flash, or JTAG), bus width, and endian mode |
| CLKIN | Differential system clock input | Accepts 33–100 MHz differential clock; feeds PLL to generate core, DDR, and peripheral clocks |
Key Features
| Feature | Design Value |
|---|---|
| Dual e500v2 Core Execution | Two independent 32-bit Power Architecture cores with 36-bit real addressing, MMU, and hardware debug support - enables SMP Linux or asymmetric RTOS partitioning |
| Hardware Security Offload | Integrated SEC processes IPSec, SSL/TLS, and SRTP in-line without CPU intervention - reduces host CPU load by >80% for encrypted traffic at 1+ Gbps |
| OCeaN Switch Fabric | Full-crossbar packet switch with priority-based reordering and starvation avoidance - ensures deterministic latency for control-plane packets amid data-plane congestion |
| Pattern Matching + DEFLATE | 16,000-regex engine with stateful rule logic (8192 rules) and hardware DEFLATE decompression - accelerates deep packet inspection and HTTP payload analysis |
| Flexible High-Speed Interconnect | Pin-multiplexed support for Serial RapidIO 1.2 (4x lane), PCI Express (x8/x4/x2/x1), or hybrid configurations - simplifies board design for multi-protocol backplanes |
| DDR3-1333 ECC Memory Subsystem | Dual 64-bit DDR3 controllers with on-die termination, auto-refresh, CKE-gated sleep, and byte-accessible ECC - delivers >10 GB/s sustained bandwidth with fault tolerance |
Applications
| Carrier-Grade Router Control Plane | Secure Media Gateway |
|---|---|
Use Scenario: Managing routing protocols (BGP, OSPF), session control, and CLI in 10G+ edge routers. IC Role / Device Role / Timing Role: Dual e500v2 cores run Linux-based control plane software while SEC handles IKEv2 key exchange and IPsec SA setup. Use Value: Hardware-accelerated crypto and OCeaN fabric enable sub-10ms control-path response under 100K+ concurrent sessions. | Use Scenario: Transcoding and encrypting VoIP/SIP media streams across multiple TDM and IP interfaces. IC Role / Device Role / Timing Role: DUART and eLBC interface legacy TDM peripherals; eTSECs handle SIP signaling and RTP transport; SEC performs real-time AES-128 encryption. Use Value: Integrated pattern matching identifies SIP headers and triggers DEFLATE decompression of SDP payloads - reducing media processing latency by 35%. |
| Industrial Firewall Appliance | Ruggedized Wireless Baseband Unit |
Use Scenario: Deep packet inspection and stateful firewalling in DIN-rail mounted industrial gateways. IC Role / Device Role / Timing Role: Pattern Matching Engine scans HTTP/HTTPS flows for malware signatures; SEC enforces TLS 1.2 decryption and re-encryption. Use Value: 16,000-regex database with cross-packet detection enables zero-day threat identification without software updates. | Use Scenario: Baseband processing and fronthaul transport in outdoor small-cell 4G/LTE units. IC Role / Device Role / Timing Role: Serial RapidIO 4x interface connects to FPGA-based PHY; DDR3 subsystem buffers IQ samples; eTSECs carry CPRI-over-Ethernet. Use Value: Deterministic OCeaN switching guarantees <5 µs jitter for CPRI timing-critical frames across multiple radio units. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8572EVTALR | Same die, 1023-pin FC-PBGA, but rated for commercial temperature (0°C to 105°C vs. extended -40°C to 105°C) | Suitable for indoor telecom equipment; lacks extended temp qualification for outdoor base stations | Select MPC8572EVTARLD when operating ambient exceeds 70°C or requires industrial-grade reliability certification |
| MPC8572EVTAJ | Same functional spec, but packaged in 1023-pin PBGA with different thermal lid construction and moisture sensitivity level (MSL 3 vs. MSL 4) | Compatible footprint but requires adjusted reflow profile and humidity handling during SMT assembly | Choose MPC8572EVTARLD for high-volume production with automated optical inspection and long-term storage requirements |
Compared with MPC8572EVTALR and MPC8572EVTAJ, the MPC8572EVTARLD provides verified extended-temperature operation and MSL 4 packaging - critical for deployment in uncontrolled environments and high-reliability manufacturing lines where thermal cycling and moisture resistance directly impact field failure rates.
Availability
MPC8572EVTARLD is available at Aetrix Electronics and suitable for carrier-grade routers, secure media gateways, and industrial firewalls requiring stable component supply, long lifecycle support, and traceable sourcing through NXP's qualified distribution channel.
Supply support for MPC8572EVTARLD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and communications markets.
The MPC8572EVTARLD belongs to NXP's PowerQUICC III family - designed specifically for high-throughput, low-latency embedded networking applications requiring integrated security, multi-protocol I/O, and deterministic real-time processing.
FAQ
What is the maximum DDR3 data rate supported by the MPC8572EVTARLD?
The MPC8572EVTARLD supports DDR3-1333 (667 MHz clock, 1333 MT/s) with 64-bit wide interfaces per controller. It implements on-die termination, auto-refresh, and CKE-gated sleep mode. The DDR3 I/O operates at 1.5 V ± 75 mV, and full ECC protection is applied on 64-bit boundaries. This enables sustained memory bandwidth exceeding 10 GB/s per controller in real-world packet buffering applications using the MPC8572EVTARLD.
Does the MPC8572EVTARLD support PCIe endpoint and root complex modes simultaneously?
No, the MPC8572EVTARLD does not support simultaneous PCIe endpoint and root complex operation across its three controllers. Each PCIe controller is individually configurable as either root complex or endpoint, but all three must operate in the same mode (all root complex or all endpoint) due to shared configuration space and transaction routing logic. This constraint is documented in Section 16 of the MPC8572EEC Rev. 7 specification and applies identically to the MPC8572EVTARLD variant.
How many crypto algorithms does the integrated Security Engine (SEC) in the MPC8572EVTARLD accelerate?
The MPC8572EVTARLD's integrated Security Engine accelerates 12 distinct cryptographic primitives: AES (ECB/CBC/CTR/GCM/CCM), DES/3DES, SHA-1/256/384/512, MD5, HMAC (all variants), RSA (up to 4096-bit), Elliptic Curve (F2m/Fp, up to 1023-bit), KEA/Kasumi (F8/F9), ARC4, and CRC-32/CRC-32C. All are implemented in dedicated execution units (AESU, DEU, MDEU, PKEU, etc.) and accessible via descriptor-based DMA - enabling concurrent algorithm execution without CPU intervention on the MPC8572EVTARLD.
What is the purpose of the OCeaN switch fabric in the MPC8572EVTARLD?
The OCeaN (On-Chip Ethernet and Networking) switch fabric in the MPC8572EVTARLD is a non-blocking, priority-aware crossbar that routes packets between internal blocks - including eTSECs, RapidIO, PCI Express, DMA engines, and memory controllers. It enables zero-copy forwarding, avoids software-mediated bottlenecks, and guarantees bounded latency (<5 µs) for time-critical control packets. Its starvation-avoidance logic ensures fair bandwidth allocation among traffic classes, making it essential for real-time networking stacks running on the MPC8572EVTARLD.
Can the MPC8572EVTARLD boot directly from SPI flash?
No, the MPC8572EVTARLD does not support direct boot from SPI flash. Its boot sequencer supports only I²C serial EEPROM (with extended addressing), NOR flash (via eLBC), NAND flash (via FCM), or JTAG. SPI flash requires external glue logic or a companion microcontroller to translate SPI commands into I²C or parallel interface signals readable by the MPC8572EVTARLD boot ROM. This limitation is explicitly stated in Section 22 (Ordering Information) and Section 5 (RESET Initialization) of the MPC8572EEC Rev. 7 datasheet for the MPC8572EVTARLD.
MPC8572EVTARLD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 1023-BFBGA, FCBGA
- Series:
- MPC85xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e500
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 1.067GHz
- Co-Processors/DSP:
- Signal Processing; SPE, Security; SEC
- RAM Controllers:
- DDR2, DDR3
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (4)
- SATA:
- -
- USB:
- -
- Voltage - I/O:
- 1.5V, 1.8V, 2.5V, 3.3V
- Operating Temperature:
- 0°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Cryptography, Random Number Generator
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 1023-FCBGA (33x33)
- Additional Interfaces:
- DUART, HSSI, I2C, RapidIO
MPC8572EVTARLD FAQ
1.How can I place an order for MPC8572EVTARLD through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC8572EVTARLD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC8572EVTARLD reliable?
The price and inventory of MPC8572EVTARLD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC8572EVTARLD is usually 5 days.
3.What payment methods are accepted for MPC8572EVTARLD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC8572EVTARLD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC8572EVTARLD?
MPC8572EVTARLD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC8572EVTARLD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC8572EVTARLD?
For technical support, including MPC8572EVTARLD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC8572EVTARLD requirements.
6.How does Aetrix verify that MPC8572EVTARLD is sourced from the original manufacturer or authorized distributors?
All MPC8572EVTARLD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC8572EVTARLD meets industry standards.
7.What is the process for return or replacement of MPC8572EVTARLD?
All MPC8572EVTARLD units undergo pre-shipment inspection (PSI). If there is an issue with MPC8572EVTARLD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC8572EVTARLD part is unused and in its original packaging.
Return procedure for MPC8572EVTARLD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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