NXP Semiconductors MPC859DSLVR66A

Overview

MPC859DSLVR66A from NXP Semiconductors (formerly Freescale) is a PowerQUICC™ II communications processor integrating a 32-bit PowerPC core, CPM-based serial peripherals, and enhanced ATM functionality. It operates at up to 66 MHz CPU frequency, features 4-Kbyte instruction and 4-Kbyte data caches, supports MII/UTOPIA dual-mode Ethernet/ATM interface, and targets DSL access concentrators and ATM edge equipment.

For engineers reviewing the MPC859DSLVR66A datasheet, MPC859DSLVR66A pinout, MPC859DSLVR66A application, or MPC859DSLVR66A equivalent, key selection criteria include its single SCC1-for-Ethernet configuration, absence of TSA and SMC2, 1.8 V core / 3.3 V I/O voltage domains, 357-pin PBGA package, and ESAR-mode OAM/PM support for DSL aggregation systems.

Technical Context

The MPC859DSLVR66A implements a single-issue PowerPC core with MMU, 32-entry ITLB/DTLB, and physically addressed caches. Its CPM includes 10 SDMA channels, one SCC (SCC1, Ethernet-only), one SMC (SMC1, UART-only), four baud rate generators, and ROM-resident AAL2/VBR support.

It integrates a Fast Ethernet Controller supporting simultaneous MII (10/100Base-T) and UTOPIA Level 2 operation, IEEE 1149.1 JTAG debug interface, and SIU with clock synthesizer, PIT, watchdog, and bus monitor - all operating under strict 1.8 V core and 3.3 V I/O power sequencing requirements.

Key Specifications

Pinout & Package

357-pin Plastic Ball Grid Array (PBGA), 27 × 27 mm body, 1.27 mm pitch, RoHS-compliant. Thermal pad on underside requires soldered connection to internal ground plane for thermal performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar communications processor applications.

Compared with MPC859TFR66A and MPC866TFR66A, the MPC859DSLVR66A trades peripheral breadth for DSL-specific efficiency: it removes unused TSA/SMC2 logic to reduce die size and dynamic power, while retaining hardware-accelerated ESAR and AAL2 essential for broadband access equipment.

Availability

MPC859DSLVR66A is available at Aetrix Electronics and suitable for DSL access concentrators, ATM edge routers, residential gateways, and legacy TDM-to-ATM bridge systems requiring stable component supply across extended product lifecycles.

Supply support for MPC859DSLVR66A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and communication infrastructure markets.

The MPC859DSLVR66A belongs to the PowerQUICC™ II family, designed specifically for cost-sensitive, high-reliability DSL and ATM access equipment requiring integrated SAR, Ethernet, and low-power operation.

FAQ

What is the maximum operating frequency of the MPC859DSLVR66A?

The MPC859DSLVR66A operates at a maximum CPU frequency of 66 MHz in 1:1 bus mode. At this speed, it achieves 66 MHz core execution while maintaining a synchronous 66 MHz bus interface. The device supports 2:1 mode (e.g., 133 MHz CPU with 66 MHz bus), but MPC859DSLVR66A is rated and characterized only for 66 MHz operation - higher frequencies require MPC859DSLVR133A or equivalent variants.

Does the MPC859DSLVR66A support UTOPIA Level 2 operation?

Yes, the MPC859DSLVR66A supports UTOPIA Level 2 compliant interface with added FIFO buffering to reduce total cell transmission time. It also maintains backward compatibility with UTOPIA Level 1. This capability is implemented in hardware within the ESAR block and is used exclusively via SCC1 when configured for UTOPIA master/slave operation - no software microcode is required.

Why does the MPC859DSLVR66A lack a Time Slot Assigner (TSA)?

The MPC859DSLVR66A omits the TSA to reduce silicon area, power consumption, and design complexity for DSL-specific applications that do not require TDM multiplexing. As confirmed in Freescale's Hardware Specifications Rev. 2, Figure 2 and Table 1, TSA is excluded from MPC859DSL variants. This allows tighter timing closure and lower static power - critical for fanless DSLAM line cards.

Can the MPC859DSLVR66A be used with a 5-V tolerant PHY interface?

Yes, selected MPC859DSLVR66A pins - including PA[0:15], PB[14:31], PC[4:15], PD[3:15], MII_TXEN, and MII_MDIO - are 5-V tolerant, provided the input voltage does not exceed VDDH + 2.5 V (i.e., ≤5.965 V at max VDDH). However, the device itself operates at 3.3 V I/O and 1.8 V core; external level-shifting is unnecessary for 5-V PHYs meeting this constraint.

What debug interfaces are supported by the MPC859DSLVR66A?

The MPC859DSLVR66A supports IEEE 1149.1 JTAG boundary-scan and on-chip emulation via TMS, TCK, TDO, TDI, and TRST_B pins. It includes eight hardware comparators (four instruction address, two data address, two data value) for breakpoint generation, enabling non-intrusive firmware debugging and flash programming without halting real-time ATM processing.