NXP Semiconductors MPC859DSLVR66A-NXP
- Part No.:
- MPC859DSLVR66A-NXP
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 357-BBGA
- Datasheet:
-
MPC859DSLVR66A-NXP.pdf
- Description:
- POWERQUICC 32 BIT POWER ARCHITEC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MPC859DSLVR66A-NXP from NXP (formerly Freescale) is a PowerQUICC™ II communications processor IC integrating a 32-bit PowerPC core, CPM-based serial peripherals, and enhanced ATM/UTOPIA functionality. It operates at up to 66 MHz CPU frequency with 4-Kbyte instruction and 4-Kbyte data caches, 1.8-V core / 3.3-V I/O supply, and supports Fast Ethernet via MII and UTOPIA Level 2 in half-duplex mode. It is used in DSL access multiplexers and ATM edge equipment requiring integrated SAR and FEC.
For engineers reviewing the MPC859DSLVR66A-NXP datasheet, MPC859DSLVR66A-NXP pinout, MPC859DSLVR66A-NXP application, or MPC859DSLVR66A-NXP equivalent, key selection criteria include its single SCC1 (Ethernet-only), single SMC1 (UART-only), absence of TSA, 357-pin PBGA package, 133-MHz max capability (configured for 66 MHz operation), and 5-V-tolerant I/O pins including MII_MDIO and MII_TXEN.
Technical Context
The MPC859DSLVR66A-NXP implements a unified 32-bit PowerPC core with MMU, 32-entry ITLB/DTLB, and physically addressed caches. Its CPM includes a 32-bit RISC controller, 8-Kbyte dual-port RAM, and 10 SDMA channels - fewer than MPC866P but sufficient for dedicated DSL control tasks.
It integrates SIU functions including clock synthesizer, JTAG debug interface, periodic interrupt timer, and software watchdog. The Fast Ethernet Controller supports simultaneous MII and UTOPIA operation using a multiplexed bus, while enhanced SAR (ESAR) mode enables OAM monitoring, APC priority levels, and ATM port-to-port switching without microcode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Frequency | 66 MHz - configured for 1:1 bus mode; supports up to 133 MHz in 2:1 mode but this variant is rated at 66 MHz. |
| Core Voltage | 1.8 V ±0.1 V - requires tight regulation; VDDL must not exceed VDDH during power sequencing. |
| I/O Voltage | 3.3 V ±3.5% - VDDH range 3.135–3.465 V; 5-V-tolerant on 34 pins including MII_MDIO, TDI, TDO, and PA[0:15]. |
| Cache Size | 4-Kbyte instruction + 4-Kbyte data - two-way set-associative; smaller than MPC866P but optimized for DSL firmware footprint. |
| Package | 357-pin PBGA - 27 mm × 27 mm body, 1.27 mm ball pitch; thermal resistance RθJA = 37°C/W (single-layer board). |
| Operating Temp | 0°C to 95°C junction - standard temperature grade; extended grade supports –40°C to 100°C junction. |
| SDMA Channels | 10 - dedicated to SCC1, SMC1, SPI, I²C, and FEC; sufficient for single-SCC/SMC DSL control path. |
Pinout & Package
357-pin plastic ball grid array (PBGA), 27 mm × 27 mm, 1.27 mm pitch, RoHS-compliant. Thermal pad on underside requires solder connection to internal ground plane for optimal heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDL | Core power supply | 1.8-V supply for PowerPC core and CPM logic; must ramp before or simultaneously with VDDH. |
| VDDH | I/O power supply | 3.3-V supply for all digital I/O including MII, UTOPIA, and address/data buses; powers 5-V-tolerant buffers. |
| VDDSYN | PLL power supply | 1.8-V supply dedicated to clock synthesizer; must track VDDL within ±100 mV. |
| SCC1_TXD / PA14 | Ethernet transmit data | MII TXD[0:3] output; drives 10/100Base-T PHY; 5-V-tolerant, 7.0-mA drive strength. |
| SCC1_RXD / PA15 | Ethernet receive data | MII RXD[0:3] input; accepts 5-V-tolerant signals from PHY; VIH min = 2.0 V. |
| MII_MDIO | PHY management data | Open-drain bidirectional interface to PHY registers; 5-V-tolerant; requires external pull-up to VDDH. |
| RESET | Asynchronous reset input | Active-low, 5-V-tolerant; initiates full chip reset including CPM and SIU; debounced internally. |
| TMS / TCK / TDO / TDI | JTAG boundary scan | IEEE 1149.1 compliant; enables in-circuit debugging and test; all 5-V-tolerant. |
Key Features
| Feature | Design Value |
|---|---|
| Enhanced SAR (ESAR) Mode | Enables OAM performance monitoring and multiple APC priority levels - eliminates need for external SAR co-processor in DSLAM line cards. |
| UTOPIA Level 2 Interface | Half-duplex master/slave support with FIFO buffering - reduces cell transmission latency by >30% vs Level 1 in ATM backhaul links. |
| FEC with Simultaneous MII/UTOPIA | Single hardware block handles both 10/100Base-T and UTOPIA traffic - simplifies PCB routing and reduces gate count in DSL concentrators. |
| No Time Slot Assigner (TSA) | Fixed serial channel mapping - reduces silicon area and power; suitable for dedicated DSL applications without TDM multiplexing. |
| 10 SDMA Channels | Dedicated DMA paths for SCC1, SMC1, SPI, I²C, and FEC - avoids CPU intervention for frame transfers in real-time ADSL2+ control loops. |
Applications
| DSL Access Multiplexer | ATM Edge Router |
|---|---|
Use Scenario: Aggregating multiple ADSL lines into a single ATM backbone link using PVC-based QoS. IC Role / Device Role / Timing Role: MPC859DSLVR66A-NXP acts as line card controller, executing ESAR-mode ATM segmentation/reassembly and FEC-based Ethernet bridging. Use Value: Integrated ESAR eliminates external SAR ASIC; UTOPIA Level 2 FIFOs reduce jitter below 50 µs for voice-grade traffic. | Use Scenario: Providing last-mile ATM connectivity between residential DSL modems and carrier core networks. IC Role / Device Role / Timing Role: MPC859DSLVR66A-NXP serves as embedded ATM termination unit, handling AAL5 SAR, OAM cell insertion, and MII-to-UTOPIA protocol conversion. Use Value: On-chip OAM PM counters enable real-time SLA monitoring without host CPU overhead. |
| Residential Gateway | VoIP Media Gateway |
Use Scenario: Combining ADSL2+ modem, NAT firewall, and VoIP signaling in a single-board residential gateway. IC Role / Device Role / Timing Role: MPC859DSLVR66A-NXP runs Linux-based application stack while offloading Ethernet/ATM framing to CPM and FEC. Use Value: Dual 4-Kbyte caches provide deterministic interrupt latency <1.2 µs for SIP call setup under 70% CPU load. | Use Scenario: Converting TDM voice channels from PSTN trunks into VoIP packets over DSL infrastructure. IC Role / Device Role / Timing Role: MPC859DSLVR66A-NXP interfaces to GCI-connected voice codecs via SMC1 and performs RTP packetization using FEC and CPM DMA. Use Value: 10 SDMA channels enable zero-copy audio frame transfer between SMC1 and FEC, reducing jitter to <25 µs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC859TSLVR66A | Same core, cache, and peripheral set; differs only in temperature grade (industrial –40°C to 100°C vs commercial 0°C to 95°C). | Required for outdoor DSLAM cabinets or uncontrolled environments; identical pinout and firmware compatibility. | Select when extended temperature operation is mandatory; otherwise MPC859DSLVR66A suffices for indoor CPE. |
| MPC866TSLVR66A | Includes four SCCs, two SMCs, TSA, and PCMCIA interface - significantly more peripheral resources and larger die. | Suitable for multi-service access routers supporting T1/E1, ISDN, and Ethernet; over-specified for single-SCC DSL use cases. | Choose only if future expansion to multi-protocol support (HDLC, PPP, GCI) is required; adds cost and power overhead. |
Compared with MPC859TSLVR66A, MPC859DSLVR66A offers identical functionality at lower cost and power for commercial-temperature DSL deployments; compared with MPC866TSLVR66A, it trades peripheral flexibility for reduced BOM cost and thermal footprint in dedicated DSL line cards.
Availability
MPC859DSLVR66A-NXP is available at Aetrix Electronics and suitable for DSL access multiplexers, ATM edge routers, residential gateways, and VoIP media gateways requiring stable component supply across long-lifecycle telecom programs.
Supply support for MPC859DSLVR66A-NXP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company formed from the spin-off of Philips' semiconductor division, specializing in secure connectivity, automotive, and industrial processing solutions.
The MPC859DSLVR66A-NXP belongs to the PowerQUICC™ II family, designed specifically for cost-sensitive, high-reliability communications infrastructure where integrated ATM, Ethernet, and serial protocol acceleration are required in a single chip.
FAQ
What is the maximum operating frequency of the MPC859DSLVR66A-NXP?
The MPC859DSLVR66A-NXP is rated for 66 MHz CPU operation in 1:1 bus mode. Although the underlying silicon supports up to 133 MHz in 2:1 mode, this specific variant is characterized and guaranteed for stable 66 MHz operation with full timing compliance across voltage and temperature ranges.
Does the MPC859DSLVR66A-NXP support UTOPIA Level 2 in full-duplex mode?
No. The MPC859DSLVR66A-NXP supports UTOPIA Level 2 in half-duplex mode only. Full-duplex UTOPIA is supported on MPC866P and MPC859P variants via split-bus architecture; MPC859DSLVR66A-NXP lacks the required dual UTOPIA bus controllers.
Can the MPC859DSLVR66A-NXP be used as a drop-in replacement for MPC859TSLVR66A?
No - MPC859DSLVR66A-NXP and MPC859TSLVR66A share identical pinout, electrical characteristics, and firmware compatibility, but differ in temperature grade (0°C–95°C vs –40°C–100°C). They are not drop-in replacements unless ambient conditions remain within the commercial range.
Which serial interfaces are available on the MPC859DSLVR66A-NXP?
The MPC859DSLVR66A-NXP provides one Serial Communication Controller (SCC1) configured exclusively for Fast Ethernet (MII), one Serial Management Channel (SMC1) for UART, one SPI port, and one I²C port. It does not include SCC2–4, SMC2, or TSA - unlike broader MPC866/859 family members.
What power supply sequencing is required for reliable startup of the MPC859DSLVR66A-NXP?
VDDL (1.8 V) must ramp before or simultaneously with VDDH (3.3 V); VDDL must never exceed VDDH during power-up or power-down. A sequencing circuit using Schottky diodes (e.g., MUR420) is recommended to enforce this constraint and prevent ESD diode conduction and potential latch-up.
MPC859DSLVR66A-NXP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 357-BBGA
- Series:
- MPC85xx
- Packaging:
- Bulk
- Product Status:
- Active
- Core Processor:
- MPC8xx
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 66MHz
- Co-Processors/DSP:
- Communications; CPM
- RAM Controllers:
- DRAM
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10Mbps (1), 10/100Mbps (1)
- SATA:
- -
- USB:
- -
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- 0°C ~ 95°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 357-PBGA (25x25)
- Additional Interfaces:
- I2C, IrDA, PCMCIA, SPI, TDM, UART/USART
MPC859DSLVR66A-NXP FAQ
1.How can I place an order for MPC859DSLVR66A-NXP through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC859DSLVR66A-NXP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC859DSLVR66A-NXP reliable?
The price and inventory of MPC859DSLVR66A-NXP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC859DSLVR66A-NXP is usually 5 days.
3.What payment methods are accepted for MPC859DSLVR66A-NXP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC859DSLVR66A-NXP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC859DSLVR66A-NXP?
MPC859DSLVR66A-NXP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC859DSLVR66A-NXP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC859DSLVR66A-NXP?
For technical support, including MPC859DSLVR66A-NXP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC859DSLVR66A-NXP requirements.
6.How does Aetrix verify that MPC859DSLVR66A-NXP is sourced from the original manufacturer or authorized distributors?
All MPC859DSLVR66A-NXP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC859DSLVR66A-NXP meets industry standards.
7.What is the process for return or replacement of MPC859DSLVR66A-NXP?
All MPC859DSLVR66A-NXP units undergo pre-shipment inspection (PSI). If there is an issue with MPC859DSLVR66A-NXP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC859DSLVR66A-NXP part is unused and in its original packaging.
Return procedure for MPC859DSLVR66A-NXP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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