My Inquiry
My Account
NXP Semiconductors MPC859TVR133A
- Part No.:
- MPC859TVR133A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 357-BBGA
- Datasheet:
-
MPC859TVR133A.pdf
- Description:
- IC MPU MPC8XX 133MHZ 357BGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,103
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MPC859TVR133A from Freescale Semiconductor is a 32-bit PowerQUICC™ communications processor integrating a PowerPC core, CPM, and SIU in a single PBGA package. It operates at 133 MHz CPU frequency (2:1 bus mode), features 4-Kbyte instruction and 4-Kbyte data caches, supports one Fast Ethernet controller (MII/UTOPIA), and targets ATM edge and DSL access concentrator applications.
For engineers reviewing the MPC859TVR133A datasheet, MPC859TVR133A pinout, MPC859TVR133A application, or MPC859TVR133A equivalent, key selection criteria include its 1.8 V core / 3.3 V I/O supply, 357-pin PBGA package, IEEE 1149.1 JTAG debug support, and ESAR-enhanced ATM functionality with OAM/PM and UTOPIA Level 2 compliance.
Technical Context
The MPC859TVR133A implements a single-issue 32-bit PowerPC core with MMU, 32-entry ITLB/DTLB, and physically addressed caches. Its CPM includes a 32-bit RISC controller, 8-Kbyte dual-port RAM, and 10 SDMA channels for serial peripheral offload.
It integrates a System Integration Unit (SIU) with clock synthesizer, software watchdog, PIT, IEEE 1149.1 TAP controller, and memory controller supporting DRAM, SDRAM, SRAM, and flash. The FEC supports simultaneous MII and UTOPIA operation, while ESAR mode enables ATM port-to-port switching without microcode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Frequency | 133 MHz - Enables high-throughput packet processing in DSLAM and ATM aggregation nodes. |
| Core Voltage | 1.7–1.9 V - Requires tightly regulated low-noise core supply; sequencing must prevent VDDL > VDDH during power-up. |
| I/O Voltage | 3.135–3.465 V - Supports 3.3 V logic with 5-V tolerant pins (e.g., PA[0:15], MII_MDIO) up to 5.5 V. |
| Cache Size | 4-Kbyte instruction + 4-Kbyte data - Two-way set-associative, lockable per cache block; optimized for deterministic real-time control. |
| Package | 357-pin PBGA - 27 × 27 mm body, 1.27 mm ball pitch; requires four-layer PCB with dedicated VDD/GND planes. |
| Thermal Limit | Junction max 95 °C (standard temp grade) - Thermal design must use RθJB = 13 °C/W model with board-level heat spreading. |
| Power Dissipation | 260 mW typical / 320 mW max at 133 MHz - Excludes I/O driver power; actual system dissipation depends on external buffer loading. |
Pinout & Package
357-pin plastic ball grid array (PBGA), 27 mm × 27 mm, 1.27 mm ball pitch, RoHS-compliant. Package code VR indicates standard temperature grade (0 °C to 95 °C junction).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDL | Core power supply | 1.8 V nominal; must be sequenced before VDDH and held within ±100 mV of VDDSYN. |
| VDDH | I/O power supply | 3.3 V nominal; powers all digital I/O including MII, UTOPIA, and parallel interface; 5-V tolerant pins require external clamping if driven above VDDH + 2.5 V. |
| VDDSYN | PLL power supply | 1.8 V nominal; supplies clock synthesizer; noise sensitivity demands dedicated low-ESR decoupling near PLL pins. |
| TMS, TCK, TDI, TDO, TRST_B | JTAG test access port | IEEE 1149.1 compliant; enables boundary-scan testing and on-chip emulation debugging. |
| MII_TXD[0:3], MII_TX_EN, MII_RXD[0:3], MII_RX_ER | FEC MII interface | Direct connection to 10/100Base-T PHY; requires controlled-impedance 50 Ω traces and <6" length for signal integrity. |
| UTOPIA_CLK, UTOPIA_DATA[0:7], UTOPIA_CTRL | UTOPIA Level 2 interface | Half-duplex or full-duplex master/slave operation; supports ATM cell transmission with FIFO buffering to reduce latency. |
| SCC1_TXD/SCC1_RXD | Serial Communication Controller 1 | Dedicated to Ethernet on MPC859T variants; implements HDLC/PPP framing for management channel or backup link. |
Key Features
| Feature | Design Value |
|---|---|
| Enhanced SAR (ESAR) mode | Enables ATM OAM/PM, multi-PHY support, and port-to-port switching without RAM-based microcode - reduces boot dependency and improves determinism. |
| Fast Ethernet Controller (FEC) | Simultaneous MII and UTOPIA operation allows concurrent 10/100Base-T LAN access and ATM backhaul - eliminates need for external switch fabric. |
| CPM with 10 SDMA channels | Offloads serial protocol handling (HDLC, UART, IrDA, BISYNC) from main CPU - preserves 133 MHz core cycles for packet classification and QoS scheduling. |
| Memory controller with 8 banks | Glueless interface to SDRAM, DRAM, SRAM, and flash; supports variable block sizes (32 KB–256 MB) and programmable wait states - simplifies BOM and layout for multi-memory systems. |
| IEEE 1149.1 JTAG debug | Full boundary-scan and real-time instruction/data watchpoint debugging - accelerates bring-up and validation of time-critical communications firmware. |
Applications
| DSL Access Concentrator | ATM Edge Router |
|---|---|
|
Use Scenario: Aggregating multiple ADSL lines into a single ATM uplink for service provider central office. IC Role / Device Role / Timing Role: Main control and packet forwarding engine; manages SAR segmentation/reassembly, QoS policing, and OAM cell insertion. Use Value: ESAR mode enables hardware-accelerated ATM switching and OAM performance monitoring - reduces latency jitter and eliminates microcode update dependencies. |
Use Scenario: Providing Layer 2 bridging and traffic shaping at metro ATM network edge. IC Role / Device Role / Timing Role: Communications processor executing SAR, FEC, and CPM-managed serial protocols; synchronizes UTOPIA and MII clocks via internal clock synthesizer. Use Value: Dual-interface capability (MII + UTOPIA) allows simultaneous LAN-side Ethernet and WAN-side ATM connectivity - avoids external bridge ICs and reduces bill-of-materials cost. |
| Industrial Protocol Gateway | Legacy Telecom Interface Card |
|
Use Scenario: Translating Modbus TCP over Ethernet to HDLC/PPP over T1/E1 in SCADA backhaul. IC Role / Device Role / Timing Role: Host processor running real-time OS; uses SCC1 for Ethernet and SMC1/SMC2 for UART/GCI serial links to field devices. Use Value: Integrated CPM with 10 SDMA channels handles concurrent serial protocols without CPU intervention - ensures deterministic response under heavy I/O load. |
Use Scenario: Replacing aging MC68360-based line cards in carrier-class TDM switches. IC Role / Device Role / Timing Role: Drop-in upgrade path with compatible PIP and PCMCIA interfaces; leverages existing Centronics and socket firmware. Use Value: Pin-compatible replacement for MPC859T with identical 357-PBGA footprint and memory controller timing - minimizes PCB redesign effort and qualification cycle. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC859PVR133A | 16-Kbyte instruction cache + 8-Kbyte data cache; 16 virtual serial channels vs. 10 SDMA on MPC859T. | Higher cache bandwidth suits complex routing stacks; supports additional SCC/SMC peripherals not used on MPC859T. | Select when application requires larger instruction working set or expanded serial I/O beyond single SCC/SMC configuration. |
| MPC866TVR133A | Four SCCs (vs. one on MPC859T); supports up to four Ethernet ports via MII multiplexing; no TSA. | Targeted at multi-port Ethernet/ATM gateway; lacks DSL-specific optimizations like single-SCC Ethernet focus. | Choose for designs needing multiple independent Ethernet interfaces or broader serial peripheral count, accepting higher pin count and power. |
Compared with MPC859PVR133A and MPC866TVR133A, the MPC859TVR133A offers optimal balance of ATM/DSL feature density, thermal efficiency (320 mW max), and minimal peripheral footprint - making it ideal for space-constrained, cost-sensitive access concentrators where single-Ethernet + UTOPIA is sufficient.
Availability
MPC859TVR133A is available at Aetrix Electronics and suitable for DSL access concentrators, ATM edge routers, industrial protocol gateways, and legacy telecom interface cards requiring stable component supply across extended product lifecycles.
Supply support for MPC859TVR133A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Freescale Semiconductor (now part of NXP Semiconductors) is a fabless semiconductor company specializing in embedded processing, networking, and automotive ICs.
The MPC859TVR133A belongs to the PowerQUICC™ family - designed specifically for cost-effective, low-power communications infrastructure requiring integrated ATM, Ethernet, and serial protocol acceleration in a single chip.
FAQ
What is the maximum operating junction temperature for MPC859TVR133A?
The MPC859TVR133A has a maximum junction temperature of 95 °C under standard temperature grade operation. This rating assumes proper thermal design using the junction-to-board thermal resistance (RθJB = 13 °C/W) and a four-layer PCB with ground/power planes. Exceeding this limit risks reliability degradation and functional failure; thermal margin must be verified under worst-case ambient and power conditions in the final system.
Does MPC859TVR133A support UTOPIA Level 2 in full-duplex mode?
Yes, the MPC859TVR133A supports full-duplex UTOPIA Level 2 operation in both master (ATM side) and slave (PHY side) configurations using a split-bus architecture. This capability is enabled in ESAR mode and allows simultaneous cell transmission and reception without FIFO overflow - critical for low-latency ATM backhaul in DSLAM applications.
How many serial DMA channels does MPC859TVR133A provide?
The MPC859TVR133A provides 10 serial DMA (SDMA) channels within its Communications Processor Module (CPM). These channels handle autonomous data movement for SCC1, SMC1, SMC2, SPI, and I²C peripherals - freeing the 133 MHz PowerPC core for higher-layer protocol processing and application logic execution.
Is MPC859TVR133A pin-compatible with other MPC859 variants?
Yes, the MPC859TVR133A shares the same 357-pin PBGA package and pinout with MPC859PVR133A and MPC859DSLVR133A. However, functional differences exist: MPC859P includes larger caches and more SDMA channels, while MPC859DSL omits TSA and dedicates SCC1 exclusively to Ethernet. PCB layout is interchangeable, but firmware and power sequencing must match the specific variant's capabilities.
What power supply sequencing is required for MPC859TVR133A?
MPC859TVR133A requires strict voltage sequencing: VDDL (core) must ramp before VDDH (I/O) and must never exceed VDDH during power-up or power-down. The difference between VDDL and VDDSYN must remain ≤100 mV. Failure to comply risks forward-biasing ESD protection diodes and permanent damage. A discrete sequencing circuit using Schottky and rectifier diodes (per Figure 4 in Freescale's Hardware Specifications) is recommended for robust implementation.
MPC859TVR133A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 357-BBGA
- Series:
- MPC8xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- MPC8xx
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 133MHz
- Co-Processors/DSP:
- Communications; CPM
- RAM Controllers:
- DRAM
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10Mbps (1), 10/100Mbps (1)
- SATA:
- -
- USB:
- -
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- 0°C ~ 95°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 357-PBGA (25x25)
- Additional Interfaces:
- HDLC/SDLC, I2C, IrDA, PCMCIA, SPI, TDM, UART/USART
MPC859TVR133A FAQ
1.How can I place an order for MPC859TVR133A through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC859TVR133A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC859TVR133A reliable?
The price and inventory of MPC859TVR133A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC859TVR133A is usually 5 days.
3.What payment methods are accepted for MPC859TVR133A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC859TVR133A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC859TVR133A?
MPC859TVR133A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC859TVR133A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC859TVR133A?
For technical support, including MPC859TVR133A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC859TVR133A requirements.
6.How does Aetrix verify that MPC859TVR133A is sourced from the original manufacturer or authorized distributors?
All MPC859TVR133A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC859TVR133A meets industry standards.
7.What is the process for return or replacement of MPC859TVR133A?
All MPC859TVR133A units undergo pre-shipment inspection (PSI). If there is an issue with MPC859TVR133A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC859TVR133A part is unused and in its original packaging.
Return procedure for MPC859TVR133A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MPC859TVR133A Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
