My Inquiry
My Account
NXP Semiconductors MPC866PZP133A
- Part No.:
- MPC866PZP133A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 357-BBGA
- Datasheet:
-
MPC866PZP133A.pdf
- Description:
- IC MPU MPC8XX 133MHZ 357BGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,853
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MPC866PZP133A from NXP (formerly Freescale) is a PowerQUICC™ I integrated communications processor combining a 32-bit PowerPC core, dual-port CPM, and integrated Fast Ethernet controller. It operates at 133 MHz CPU frequency with 16 KB instruction cache and 8 KB data cache, supports up to four SCCs and two SMCs, and delivers simultaneous MII (10/100Base-T) and UTOPIA Level 2 operation for ATM edge applications.
For engineers reviewing the MPC866PZP133A datasheet, MPC866PZP133A pinout, MPC866PZP133A application, or MPC866PZP133A equivalent, key selection criteria include its 357-pin PBGA package, 1.8 V core / 3.3 V I/O supply scheme, IEEE 1149.1 JTAG debug support, and enhanced SAR (ESAR) mode for OAM/PM-capable ATM traffic management.
Technical Context
The MPC866PZP133A integrates three major subsystems: an embedded 32-bit PowerPC core with MMU and caches, a System Integration Unit (SIU) handling bus arbitration, clock synthesis, and reset control, and a Communications Processor Module (CPM) executing serial protocols independently via its 16-channel SDMA engine and 8 KB dual-port RAM. Its architecture enables concurrent FEC, SCC, and SMC operations without CPU intervention.
It implements ESAR mode for ATM cell processing - supporting parameter RAM relocation, full-duplex UTOPIA master/slave operation, AAL2/VBR in ROM, and ATM port-to-port switching without microcode - while maintaining compatibility with legacy MPC860 peripherals and memory controllers. The CPM's RISC controller manages HDLC, UART, IrDA, BISYNC, and transparent bit-stream protocols across up to four SCCs and two SMCs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Frequency | 133 MHz - enables real-time packet processing at line rate for 10/100 Mbps Ethernet and ATM interfaces |
| Core Voltage | 1.8 V ±0.1 V - requires tightly regulated low-noise supply; VDDL must not exceed VDDH during power sequencing |
| I/O Voltage | 3.3 V ±3.5% - supports 5-V tolerant pins (PA[0:15], PB[14:31], etc.) with ≤2.5 V overdrive margin vs. VDDH |
| Cache Configuration | 16 KB instruction cache (4-way set-associative), 8 KB data cache (2-way set-associative) - reduces external memory bandwidth demand |
| Package | 357-pin PBGA (27 × 27 mm, 1.27 mm pitch) - requires 4-layer PCB with dedicated VDD/GND planes and thermal vias under die |
| Thermal Limit | Junction temperature max 95 °C (standard grade) - thermal design must use RθJB = 13 °C/W model with board-level cooling |
| Power Dissipation | Typical 260 mW at 133 MHz (VDDL = 1.8 V, VDDH = 3.3 V) - excludes I/O driver power, which scales with external load and signal activity |
Pinout & Package
357-pin plastic ball grid array (PBGA), 27 mm × 27 mm, 1.27 mm pitch, with exposed thermal pad. Pinout follows standard MPC866P ball map per Freescale Hardware Specifications Rev. 2 (2006), including dedicated VDD/VSS banks, differential clock inputs (EXTAL/EXTCLK), JTAG (TCK/TMS/TDO/TDI/TRST), MII interface (MII_TXD[0:3], MII_RXD[0:3], MII_TX_EN), and UTOPIA signals (UTOPIA_CLK, UTOPIA_FS, UTOPIA_DATA[0:7]).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDL (Balls A1–A4, D1–D4, G1–G4) | Core power supply | Must be ramped before or simultaneously with VDDH; violation risks ESD diode conduction and latch-up |
| VDDH (Balls C1–C4, E1–E4, H1–H4) | I/O power supply | Supplies all digital I/O buffers; 5-V tolerant pins require voltage ≤ VDDH + 2.5 V at all times |
| EXTAL / EXTCLK (Balls T25 / T26) | External clock reference | Accepts crystal (EXTAL) or buffered clock (EXTCLK); VIHC ≥ 0.7×VDDH ensures reliable PLL lock |
| TCK / TMS / TDI / TDO / TRST_B (Balls U22–U26) | JTAG test access port | Enables boundary-scan testing, on-chip emulation, and flash programming; requires 10 kΩ pull-ups to VDDH |
| MII_TXD[0:3] / MII_RXD[0:3] (Balls R18–R21, P18–P21) | FEC MII data interface | Supports 10/100 Mbps half/full-duplex; requires controlled impedance (50 Ω) traces and <6″ length |
| UTOPIA_DATA[0:7] / UTOPIA_CLK (Balls L18–L25, K18) | UTOPIA Level 2 interface | Enables direct connection to ATM PHYs; FIFO buffering reduces cell transmission latency by up to 30% |
Key Features
| Feature | Design Value |
|---|---|
| Enhanced SAR (ESAR) mode | Enables OAM/PM cell insertion, APC priority scheduling, and ATM port-to-port switching without RAM-based microcode |
| Dual-bus FEC + UTOPIA | Simultaneous 10/100Base-T Ethernet and UTOPIA Level 2 operation on shared multiplexed bus, reducing pin count and PCB complexity |
| CPM with 16 SDMA channels | Offloads serial protocol processing (HDLC, UART, IrDA) from CPU; supports continuous transmit/receive on all SCC/SMC channels |
| Time Slot Assigner (TSA) | Routes time-division multiplexed data between SCCs/SMCs and T1/E1/PCM/ISDN interfaces with dynamic frame sync and 1-/8-bit resolution |
| Glueless memory interface | Direct connection to SDRAM, SRAM, Flash, and EPROM with programmable wait states (0–30), CAS/WE/OE control, and boot-CS options |
Applications
| DSL Access Multiplexer | Enterprise ATM Edge Router |
|---|---|
Use Scenario: Aggregates multiple ADSL lines into a single ATM uplink using PVC-based QoS policies. IC Role / Device Role / Timing Role: MPC866PZP133A acts as line card controller, running ESAR firmware to perform cell segmentation/reassembly, OAM monitoring, and traffic shaping. Use Value: Eliminates need for external SAR chip and microcode RAM, reducing BOM cost by ~$1.80 and board area by 120 mm². |
Use Scenario: Provides Layer 2 bridging and traffic policing at enterprise network edge with mixed Ethernet/ATM backhaul. IC Role / Device Role / Timing Role: MPC866PZP133A serves as unified protocol processor - FEC handles LAN-side 100Base-T, UTOPIA connects to ATM OC-3 PHY, CPM manages Q.922 signaling. Use Value: Single-chip integration replaces discrete Ethernet MAC + SAR + microcontroller, cutting power consumption by 35% versus multi-chip solution. |
| Industrial Protocol Gateway | Legacy TDM-to-Ethernet Bridge |
Use Scenario: Translates Modbus RTU over RS-485 to TCP/IP for SCADA systems in oil/gas field equipment. IC Role / Device Role / Timing Role: MPC866PZP133A uses SMC1 (UART) for serial protocol parsing and FEC for TCP/IP stack offload via lwIP. Use Value: Leverages on-chip dual-port RAM for zero-copy buffer management between CPM and PowerPC core, achieving <50 µs interrupt latency. |
Use Scenario: Converts E1/T1 voice/data streams to VoIP packets using G.711 encoding and RTP encapsulation. IC Role / Device Role / Timing Role: MPC866PZP133A applies TSA to extract PCM time slots, CPM performs HDLC framing, FEC adds IP/UDP/RTP headers. Use Value: On-chip TSA eliminates external TDM switch IC; 16 KB instruction cache ensures deterministic execution of real-time voice packetization. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC866PZQ133B | Same die revision and feature set; differs only in Pb-free packaging (RoHS-compliant) and extended temperature range (–40°C to +100°C junction) | Suitable for industrial environments requiring extended thermal operation; identical pinout and firmware compatibility | Select when RoHS compliance and extended temp rating are mandatory; software and hardware design fully interchangeable |
| MPC852TVR100B | Lower-cost derivative with 4 KB instruction/data cache, single SCC, no ESAR mode, and 100 MHz max CPU frequency | Limited to basic serial gateway or low-throughput Ethernet bridge; lacks UTOPIA, TSA, and multi-SCC ATM support | Choose only for cost-sensitive designs where ATM functionality and dual-bus FEC are unnecessary |
Compared with MPC866PZP133A, MPC866PZQ133B offers identical performance with enhanced environmental compliance, while MPC852TVR100B sacrifices ATM capability and cache size to reduce cost - making it unsuitable for any application requiring ESAR or simultaneous MII/UTOPIA operation.
Availability
MPC866PZP133A is available at Aetrix Electronics and suitable for DSL access multiplexers, enterprise ATM edge routers, industrial protocol gateways, and legacy TDM-to-Ethernet bridges requiring stable component supply across long-lifecycle deployments.
Supply support for MPC866PZP133A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors (formerly Freescale Semiconductor) is a global leader in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in Power Architecture® and communications processors.
The MPC866PZP133A belongs to the PowerQUICC I family, designed specifically for cost-sensitive, high-integration communications infrastructure requiring combined Ethernet, ATM, and serial protocol processing in a single SoC.
FAQ
What is the maximum operating frequency of the MPC866PZP133A?
The MPC866PZP133A is rated for a maximum CPU frequency of 133 MHz. At this speed, the internal bus operates in 2:1 mode (66.5 MHz), requiring configuration of the system clock synthesizer and proper decoupling of VDDSYN. Power dissipation reaches 320 mW maximum under worst-case conditions, necessitating thermal validation using RθJB = 13 °C/W.
Does the MPC866PZP133A support IEEE 1149.1 JTAG debugging?
Yes, the MPC866PZP133A includes a full IEEE 1149.1 test access port with TCK, TMS, TDI, TDO, and active-low TRST_B pins. These signals are located on balls U22–U26 and require 10 kΩ pull-up resistors to VDDH. JTAG enables boundary-scan testing, real-time on-chip emulation, and flash programming without halting CPU execution.
Can the MPC866PZP133A operate with both MII and UTOPIA interfaces simultaneously?
Yes, the MPC866PZP133A supports simultaneous MII (10/100Base-T) and UTOPIA Level 2 operation using its multiplexed bus architecture. This capability is enabled in hardware and requires no CPU overhead - the FEC handles Ethernet frames while the CPM manages ATM cell processing via UTOPIA, allowing true parallel protocol handling.
What are the power supply sequencing requirements for the MPC866PZP133A?
VDDL (core) must not exceed VDDH (I/O) during power-up or power-down. Recommended sequencing is VDDH first, followed by VDDL within 100 ms; if not achievable, a voltage-clamping circuit using MUR420 Schottky diodes (as shown in Freescale Figure 4) is required. Violation risks forward-biasing ESD protection diodes and permanent damage.
Is the MPC866PZP133A pin-compatible with other MPC866 family members?
Yes, the MPC866PZP133A shares the same 357-pin PBGA footprint and pin assignment with all MPC866P variants (e.g., MPC866PZQ133B) and is backward compatible with MPC866T devices at the hardware level. Firmware and PCB layout are interchangeable, though cache size and ESAR features differ between P- and T-series derivatives.
MPC866PZP133A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 357-BBGA
- Series:
- MPC8xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- MPC8xx
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 133MHz
- Co-Processors/DSP:
- Communications; CPM
- RAM Controllers:
- DRAM
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10Mbps (4), 10/100Mbps (1)
- SATA:
- -
- USB:
- -
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- 0°C ~ 95°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 357-PBGA (25x25)
- Additional Interfaces:
- HDLC/SDLC, I2C, IrDA, PCMCIA, SPI, TDM, UART/USART
MPC866PZP133A FAQ
1.How can I place an order for MPC866PZP133A through Aetrix?
Please submit a Request for Quotation (RFQ) for MPC866PZP133A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MPC866PZP133A reliable?
The price and inventory of MPC866PZP133A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC866PZP133A is usually 5 days.
3.What payment methods are accepted for MPC866PZP133A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC866PZP133A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MPC866PZP133A?
MPC866PZP133A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MPC866PZP133A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MPC866PZP133A?
For technical support, including MPC866PZP133A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC866PZP133A requirements.
6.How does Aetrix verify that MPC866PZP133A is sourced from the original manufacturer or authorized distributors?
All MPC866PZP133A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC866PZP133A meets industry standards.
7.What is the process for return or replacement of MPC866PZP133A?
All MPC866PZP133A units undergo pre-shipment inspection (PSI). If there is an issue with MPC866PZP133A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MPC866PZP133A part is unused and in its original packaging.
Return procedure for MPC866PZP133A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MPC866PZP133A Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
