NXP Semiconductors MPC870ZT133

Overview

MPC870ZT133 from Freescale Semiconductor is a 32-bit Power Architecture™ microprocessor with integrated communications processor module (CPM), dual 10/100 Mbps Fast Ethernet controllers, USB 2.0 host/function interface, and 8-Kbyte instruction/data caches - operating at 133 MHz core frequency in 2:1 bus mode, supporting industrial networking gateways and telecom edge devices.

For engineers reviewing the MPC870ZT133 datasheet, MPC870ZT133 pinout, MPC870ZT133 application, or MPC870ZT133 equivalent, key selection criteria include its 133-MHz MPC8xx core, dual FEC with MII/RMII support, USB 2.0 full-/low-speed capability, 1.8-V core / 3.3-V I/O operation, and PBGA-256 packaging for embedded communications systems requiring deterministic real-time CPM offload.

Technical Context

The MPC870ZT133 integrates a single-issue 32-bit MPC8xx core with MMU, two-way set-associative 8-Kbyte instruction and data caches, and 32-entry ITLB/DTLB supporting 4/16/512 KB and 8 MB page sizes. Its CPM executes serial protocols independently via 8-Kbyte dual-port RAM and SDMA channels.

It features a system integration unit (SIU) with clock synthesizer, PIT, watchdog, IEEE 1149.1 JTAG debug port, and memory controller supporting DRAM, SRAM, Flash, and EPROM across eight banks with up to 30 wait states and dynamic bus sizing (8/16/32-bit).

Key Specifications

Pinout & Package

The MPC870ZT133 is housed in a 256-ball PBGA package (17 mm × 17 mm, 1.0 mm ball pitch) with thermal pad exposed on underside for board-level heat conduction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar communications processor applications.

Compared with MPC875ZT133, MPC870ZT133 removes security engine silicon area and power draw while retaining identical communication peripheral set; compared with MPC885ZQ133, it trades raw speed and modern memory interface for proven CPM determinism and lower BOM cost in serial-heavy edge nodes.

Availability

MPC870ZT133 is available at Aetrix Electronics and suitable for industrial gateways, telecom edge routers, network-attached storage appliances, and secure remote terminal units requiring stable component supply across long-life embedded programs.

Supply support for MPC870ZT133 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors) designed high-performance Power Architecture™ processors for networking, automotive, and industrial control markets.

The MPC870ZT133 belongs to the PowerQUICC™ family - engineered specifically for integrated communications processing where deterministic serial offload, dual Ethernet, and USB host functionality reduce system-level component count in edge infrastructure.

FAQ

What is the maximum operating frequency of the MPC870ZT133 core and under what bus mode?

The MPC870ZT133 core operates at a maximum frequency of 133 MHz, but only in 2:1 bus mode - meaning the external bus runs at 66.5 MHz. In 1:1 mode, the core is limited to 66 MHz or 80 MHz; this constraint is hardwired in the silicon and affects memory bandwidth planning for real-time packet buffering.

Does the MPC870ZT133 support 5-V tolerant I/O, and which pins are rated for it?

Yes, the MPC870ZT133 supports 5-V tolerant inputs on specific pins including PA[0:15], PB[14:31], PC[4:15], PD[3:15], PE[14:31], TDI, TDO, TCK, TRST, TMS, MII1_TXEN, and MII_MDIO - but voltage must not exceed VDDH + 2.5 V (i.e., ≤5.8 V when VDDH = 3.3 V), and absolute max is 5.5 V per Freescale specification.

How does the CPM in the MPC870ZT133 reduce CPU load for serial communications?

The CPM in the MPC870ZT133 contains a dedicated 32-bit RISC controller, 8-Kbyte dual-port RAM, and multiple SDMA channels that autonomously handle HDLC, UART, IrDA, and BISYNC framing - allowing the main MPC8xx core to remain idle during serial data transfer and reducing average CPU utilization by up to 40% in protocol-conversion applications.

What are the mandatory reset configuration requirements for the MPC870ZT133?

The MPC870ZT133 requires HRCW[DBGC] = binary X1 and SIUMCR[DBGC] = binary X1 programmed in boot code after HRESET deassertion; additionally, MBMR[GPLB4DIS], PAPAR[5:9]/[12:13], PADIR[5:9]/[12:13], and other port assignment/direction registers must be initialized per Table 7 in the hardware spec - failure causes undefined I/O behavior.

Can the MPC870ZT133 operate in extended temperature environments, and what is its thermal limit?

Yes, the MPC870ZT133 supports extended temperature operation with a maximum junction temperature of 100 °C (TA = –40 °C min); thermal design must maintain TJ ≤100 °C using RθJB = 20 °C/W or RθJA = 29 °C/W (4-layer board), and board-level layout must include thermal vias under the exposed pad to meet this spec reliably.