NXP Semiconductors MPC875CZT133

Overview

MPC875CZT133 from Freescale Semiconductor is a Power Architecture™-based 32-bit integrated microprocessor with embedded MPC8xx core, dual 8-Kbyte instruction/data caches, MMU, two Fast Ethernet controllers (10/100 Mbps), USB 2.0 host/function interface, and hardware security engine (AES, DES, 3DES, SHA, MD5) - deployed in secure networking gateways and industrial communications controllers.

For engineers reviewing the MPC875CZT133 datasheet, MPC875CZT133 pinout, MPC875CZT133 application, or MPC875CZT133 equivalent, key selection considerations include its 133 MHz core frequency (2:1 bus mode), 1.8 V core / 3.3 V I/O operation, 256-pin PBGA package, IEEE 802.3-compliant FECs, and mandatory reset configuration requirements for boot stability.

Technical Context

The MPC875CZT133 integrates a single-issue 32-bit MPC8xx core with 32 GPRs, branch prediction, and physically addressed two-way set-associative caches (8 KB each). Its system integration unit (SIU) provides clock synthesis, JTAG debug, PIT, and software watchdog, while the communications processor module (CPM) manages serial channels via 8 KB dual-port RAM and SDMA.

It supports two independent 10/100 Mbps Fast Ethernet controllers with MII/RMII interfaces, a full-featured USB 2.0 controller (host/function/loopback), PCMCIA 2.1 socket interface, and a dedicated security engine with AESU, DEU, and MDEU accelerators - all operating under strict power sequencing constraints (VDDL ≤ VDDH, ΔV ≤ 100 mV).

Key Specifications

Pinout & Package

The MPC875CZT133 is housed in a 256-ball PBGA package (17 mm × 17 mm, 1.0 mm ball pitch) with perimeter I/O arrangement and thermal pad center. Pin functions are defined per Freescale MPC875EC Rev. 4, Section 16.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar integrated communications processor applications.

Compared with MPC875CZT133, MPC875VR133 offers identical functionality in a RoHS-compliant package, while MPC885CZQ133 delivers significantly higher compute and interface capability at the cost of board-level redesign and software porting effort.

Availability

MPC875CZT133 is available at Aetrix Electronics and suitable for secure networking gateways, industrial Ethernet controllers, VoIP media gateways, and USB-enabled field devices requiring stable component supply across long-lifecycle deployments.

Supply support for MPC875CZT133 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors since 2015) was a pioneer in Power Architecture™ microprocessors for networking and communications infrastructure.

The MPC875CZT133 belongs to the PowerQUICC™ family - designed specifically for integrated communications processors combining real-time control, networking, and security acceleration in a single chip.

FAQ

What is the maximum operating frequency of the MPC875CZT133 core?

The MPC875CZT133 core operates at a maximum frequency of 133 MHz, but only in 2:1 bus mode (i.e., core runs at twice the external bus frequency). In this configuration, the external bus must run at 66.5 MHz. The MPC875CZT133 does not support 133 MHz in 1:1 mode - attempting to configure it as such will result in undefined behavior or failure to boot.

Does the MPC875CZT133 support USB host functionality?

Yes, the MPC875CZT133 supports full USB 2.0 host controller functionality, including control, bulk, interrupt, and isochronous transfers at both 12 Mbps (full-speed) and 1.5 Mbps (low-speed). Low-speed operation requires an external hub, and the host mode includes local loopback diagnostics at 12 Mbps - a feature confirmed in Freescale MPC875EC Rev. 4, Section 2.

What are the mandatory power sequencing requirements for the MPC875CZT133?

The MPC875CZT133 requires strict voltage sequencing: VDDL (core) must never exceed VDDH (I/O) during power-up or power-down, and the difference between VDDL and VDDSYN (PLL) must remain below 100 mV. Violation risks forward-biasing ESD diodes and permanent damage. Freescale recommends using Schottky diodes (e.g., MUR420) in the sequencing circuit per Figure 4 of MPC875EC Rev. 4.

Is the MPC875CZT133 pin-compatible with the MPC870 series?

No, the MPC875CZT133 is not pin-compatible with the MPC870. Although both use the same 256-ball PBGA package, the MPC875 includes a security engine, TSA, and additional I/O routing that alters pin assignments - particularly for crypto-related signals (e.g., CHA_CLK, CHA_DATA) and TSA control lines (TS, TA, TEA). Pinout differences are documented in Tables 1 and 7 of MPC875EC Rev. 4.

What debug interfaces does the MPC875CZT133 provide?

The MPC875CZT133 provides IEEE 1149.1 JTAG (TMS, TCK, TDI, TDO, TRST) for boundary-scan testing and on-chip emulation, plus eight hardware watchpoint comparators (four instruction address, two data address, two data value) for advanced breakpoint and trace capabilities. These features are fully operational in both normal and debug modes, as specified in Sections 2 and 12 of MPC875EC Rev. 4.