NXP Semiconductors MPC880CVR133

Overview

MPC880CVR133 from Freescale Semiconductor is a PowerQUICC family integrated communications processor combining a 133 MHz MPC8xx core, dual 10/100 Fast Ethernet controllers (FEC), USB 2.0 full-/low-speed interface, UTOPIA L2-compliant ATM interface, and two serial management channels (SMCs) - all in a single 357-pin PBGA package. It targets embedded networking systems requiring deterministic real-time control, ATM edge routing, and secure wired connectivity.

For engineers reviewing the MPC880CVR133 datasheet, MPC880CVR133 pinout, MPC880CVR133 application, or MPC880CVR133 equivalent, key selection criteria include its 133 MHz core frequency (2:1 bus mode only), 1.8 V core / 3.3 V I/O operation, absence of on-chip security engine, and support for MII/RMII, UTOPIA, and SPI/I²C peripheral interfaces.

Technical Context

The MPC880CVR133 implements a 32-bit Power Architecture–compliant RISC core with 8 KB instruction and 8 KB data caches (two-way set-associative), 32-entry ITLB/DTLB, and MMU supporting 4/16/512 KB and 8 MB page sizes. Its system integration unit (SIU) provides clock synthesis, periodic interrupt timer, software watchdog, and IEEE 1149.1 JTAG test access.

The communications processor module (CPM) includes an independent 32-bit RISC controller, 8 KB dual-port RAM, four baud rate generators, and support for HDLC, UART, IrDA, BISYNC, and transparent serial protocols via three SCCs and two SMCs. Unlike the MPC885, it omits the hardware security engine (AESU/DEU/MDEU) and third Ethernet controller.

Key Specifications

Pinout & Package

Package: 357-ball PBGA (27 mm × 27 mm, 1.27 mm pitch), RoHS-compliant, lead-free finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar communications processor applications.

Compared with MPC885CVR133, MPC880CVR133 removes security hardware and one FEC to reduce cost and power, while retaining full UTOPIA L2, TSA, and dual-FEC functionality essential for ATM edge deployment; compared with MPC875VR133, it adds critical ATM infrastructure blocks absent in the lower-tier part.

Availability

MPC880CVR133 is available at Aetrix Electronics and suitable for DSLAM line cards, ATM edge routers, industrial protocol gateways, and secure network appliances requiring stable component supply across long-lifecycle deployments.

Supply support for MPC880CVR133 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors) is a fabless semiconductor company specializing in embedded processors, analog, and connectivity solutions for automotive, industrial, and networking markets.

The MPC880CVR133 belongs to the PowerQUICC family of integrated communications processors designed specifically for cost-optimized ATM, TDM, and Ethernet edge infrastructure where deterministic real-time control and multi-protocol serial I/O are required.

FAQ

What is the maximum supported bus frequency for MPC880CVR133 at 133 MHz core speed?

The MPC880CVR133 operates exclusively in 2:1 bus mode when running at 133 MHz core frequency, resulting in a maximum external bus frequency of 66.5 MHz. It does not support 1:1 bus mode at this core speed - attempting to configure 1:1 mode will cause undefined behavior or failure to boot. The 66.5 MHz bus clock is derived directly from the PLL output and must be distributed with controlled impedance routing to meet setup/hold timing for DRAM and peripheral interfaces.

Does MPC880CVR133 include a hardware security engine like the MPC885?

No, MPC880CVR133 does not include the hardware security engine present in the MPC885. It lacks the AESU, DEU, and MDEU crypto accelerators, as well as the crypto-channel and controller. This omission is intentional per the MPC885/MPC880 family differentiation: MPC880CVR133 targets applications requiring ATM and Ethernet connectivity without cryptographic offload, reducing die size, power consumption, and cost. Software-based IPsec or SSL must be implemented in the MPC880CVR133's PowerPC core if needed.

Can MPC880CVR133 support both MII and RMII simultaneously on its two FEC controllers?

Yes, MPC880CVR133 supports independent interface modes per FEC: FEC1 can operate in MII mode while FEC2 uses RMII, or vice versa. Each FEC has dedicated MII/RMII pin multiplexing controlled by SIU configuration registers (e.g., SICRH[MIIMD]). Pin assignments are mutually exclusive per controller - MII requires 18 signals (TXD[3:0], RXD[3:0], TX_EN, RX_DV, CRS, COL, TX_CLK, RX_CLK, MDIO, MDC), whereas RMII uses only 7 (TXD[1:0], TX_EN, RXD[1:0], CRS_DV, REF_CLK, MDIO, MDC). Proper pinmux and clock tree configuration is required to avoid signal contention.

What are the power sequencing requirements for MPC880CVR133 VDDL, VDDH, and VDDSYN rails?

MPC880CVR133 requires strict voltage sequencing: VDDH must ramp before VDDL and VDDSYN, and VDDL must never exceed VDDH during power-up or power-down. The difference between VDDL and VDDSYN must remain ≤100 mV at all times. Violating these conditions forward-biases internal ESD diodes, risking permanent damage. Freescale recommends using discrete Schottky diodes (e.g., MUR420) in the sequencing circuit shown in Figure 5 of the MPC885EC Rev. 7 specification to enforce safe ramp rates and voltage differentials.

Is MPC880CVR133 pin-compatible with other members of the MPC885/MPC880 family?

Yes, MPC880CVR133 is pin-compatible with MPC885CVR133 and MPC875VR133 in the 357-ball PBGA package. All share identical mechanical footprint, ball pitch, and power/ground pin assignments. However, functional pin mapping differs: MPC885CVR133 repurposes some reserved balls for security engine signals, and MPC875VR133 disables UTOPIA and TSA-related pins. PCB layout designed for MPC880CVR133 can accept MPC885CVR133 with firmware and register initialization updates, but not vice versa without hardware modification.