NXP Semiconductors MPC880VR133

Overview

MPC880VR133 from Freescale Semiconductor is a PowerQUICC II family integrated communications processor combining a 133 MHz MPC8xx core, dual 10/100 Mbps Fast Ethernet controllers (FEC), USB 2.0 full-/low-speed interface, UTOPIA L2-compliant ATM interface, and dual-port CPM with 8 KB RAM. It operates at 1.8 V core / 3.3 V I/O and targets broadband access gateways and DSLAM line cards requiring deterministic real-time packet processing.

For engineers reviewing the MPC880VR133 datasheet, MPC880VR133 pinout, MPC880VR133 application, or MPC880VR133 equivalent, key selection criteria include its 133 MHz core frequency in 2:1 bus mode, dual FEC with MII/RMII support, absence of on-chip security engine, and 357-pin PBGA package with 1.8 V/3.3 V dual-rail power architecture.

Technical Context

The MPC880VR133 implements a 32-bit Power Architecture–compliant RISC core with separate 8 KB instruction and data caches, 32-entry MMU TLBs supporting 4/16/512 KB and 8 MB page sizes, and advanced branch prediction. Its CPM includes a 32-bit RISC controller, 8 KB dual-port RAM, four baud rate generators, and serial DMA channels for SCC/SMC offload.

It integrates two independent Fast Ethernet controllers compliant with IEEE 802.3, each supporting MII and RMII physical interfaces, plus USB 2.0 function/host capability with CRC16/NRZI/bit-stuffing and 12/1.5 Mbps operation. The UTOPIA interface supports half/full-duplex L2 operation with FIFO buffering and multi-PHY support-critical for ATM cell switching without microcode.

Key Specifications

Pinout & Package

The MPC880VR133 is housed in a 357-ball PBGA package (19 × 19 mm, 1.27 mm pitch) with thermal pad. Ball assignment follows Freescale's standard MPC880 layout: VDD/VSS balls distributed across all four edges, dedicated PLL supply (VDDSYN) and reference clock inputs (EXTAL/EXTCLK), dual MII interfaces (MII1/MII2), USB D+/D−, UTOPIA data/control pins (UTOPIA_D[7:0], UTOPIA_CTRL), and 128-pin multiplexed address/data bus (A[0:31]/D[0:31]).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar communications processor applications.

Compared with MPC885VR133, MPC880VR133 removes the security engine to reduce die size, cost, and power-ideal for cost-sensitive broadband access where encryption is handled externally. Versus MPC8272CZQ133D, it trades PCI for UTOPIA and dual FEC, making it uniquely suited for fixed-line telecom infrastructure rather than general-purpose embedded computing.

Availability

MPC880VR133 is available at Aetrix Electronics and suitable for DSLAM line cards, residential gateways, VoIP media gateways, and industrial protocol converters requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for MPC880VR133 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors) is a fabless semiconductor company specializing in embedded processors, analog, and connectivity solutions for automotive, industrial, and networking markets.

The MPC880VR133 belongs to the PowerQUICC II family, designed specifically for cost-optimized, high-integration communications processors in broadband access equipment where ATM, Ethernet, and USB convergence is required without cryptographic acceleration.

FAQ

What is the maximum operating frequency of the MPC880VR133 core and under what bus mode condition?

The MPC880VR133 core operates at a maximum frequency of 133 MHz, but this is only supported in 2:1 bus mode-where the core runs at twice the external bus frequency. In 1:1 mode, the core is limited to 66 MHz or 80 MHz. This constraint is enforced by internal clock domain logic and must be configured during reset initialization via the SYPCR register. The MPC880VR133 datasheet specifies that 133 MHz operation requires strict adherence to VDDL/VDDSYN voltage tolerances (±100 mV difference) and thermal limits (TJ ≤ 100 °C).

Does the MPC880VR133 include an on-chip security engine, and how does it differ from the MPC885VR133?

No, the MPC880VR133 does not include an on-chip security engine. Unlike the MPC885VR133-which integrates AESU, DEU, and MDEU hardware accelerators-the MPC880VR133 omits this block entirely. This results in lower power consumption (typical 430 mW vs 510 mW at 133 MHz), reduced silicon area, and lower unit cost. The MPC880VR133 retains identical core, FEC, USB, UTOPIA, and CPM functionality, making it ideal for applications where cryptographic processing is handled by external ASICs or software.

What package type and ball count does the MPC880VR133 use, and are thermal pads included?

The MPC880VR133 uses a 357-ball plastic ball grid array (PBGA) package measuring 19 mm × 19 mm with 1.27 mm pitch. It includes an exposed thermal pad on the underside for enhanced heat dissipation to the PCB ground plane. The thermal pad must be soldered to a thermally optimized copper pour connected to internal ground planes via multiple vias. Freescale's hardware specification document MPC885EC Rev. 7 confirms this mechanical configuration and provides detailed land pattern recommendations for reliable thermal and electrical performance of the MPC880VR133.

Can the MPC880VR133 support both MII and RMII interfaces simultaneously on its dual Fast Ethernet controllers?

Yes, the MPC880VR133 supports independent MII and RMII operation on its two Fast Ethernet controllers (FEC1 and FEC2). Each FEC has dedicated MII signal groups (TXD[3:0], RXD[3:0], TX_EN, CRS, COL, etc.) and separate RMII pins (TXD, RXD, REF_CLK, CRS_DV), allowing one FEC to connect to a standard PHY via MII while the other connects to an RMII-capable PHY-reducing pin count and board space. This capability is documented in Section 15 (FEC Electrical Characteristics) of the MPC880VR133 hardware specification and verified in the MPC885/MPC880 reference manual.

What is the role of the Time-Slot Assigner (TSA) in the MPC880VR133, and which peripherals does it interconnect?

The Time-Slot Assigner (TSA) in the MPC880VR133 routes time-division multiplexed (TDM) data between serial peripherals-including two SCCs and two SMCs-and external TDM buses (e.g., T1, E1, ISDN). It supports 1-bit or 8-bit slot resolution, independent transmit/receive routing, and dynamic reconfiguration without stopping data flow. The TSA enables the MPC880VR133 to serve as a TDM switch or protocol converter, such as mapping PCM highway slots to SCC HDLC frames. This functionality is explicitly defined in Table 1 and Section 6.12 of the MPC880VR133 hardware specification.