NXP Semiconductors MPC9350AC

Overview

MPC9350AC from Freescale Semiconductor is a 2.5 V/3.3 V-compatible, PLL-based clock generator delivering nine low-skew LVCMOS clock outputs with frequencies up to 200 MHz and output-to-output skew ≤150 ps. It serves as a high-performance clock distribution IC for PowerQUICC II microprocessors in telecom and networking systems.

For engineers reviewing the MPC9350AC datasheet, MPC9350AC pinout, MPC9350AC application, or MPC9350AC equivalent, key selection criteria include its dual-voltage compatibility, configurable output dividers (÷2/÷4/÷8), FBSEL-selectable PLL feedback ratio (÷16/÷32), crystal or LVCMOS reference input support, and 32-lead Pb-free LQFP package.

Technical Context

The MPC9350AC employs a fully differential PLL architecture operating at VCO frequencies of 200–400 MHz, with internal feedback enabling stable multiplication of reference inputs ranging from 6.25 MHz (FBSEL=0) to 12.5 MHz (FBSEL=1). Its four independent output banks (QA–QD) are individually configured via FSELA–FSELD pins to generate exact frequency ratios relative to the VCO.

It supports static test mode (PLL_EN = low) where TCLK bypasses the PLL and routes directly to output dividers, enabling system diagnostics without PLL lock dependency. The device uses separate VCCA (PLL supply) and VCCO (I/O supply) rails to isolate analog PLL circuitry from digital switching noise, with recommended RC filtering on VCCA for noise-sensitive applications.

Key Specifications

Pinout & Package

Package: 32-lead Pb-free LQFP (7×7 mm², Case 873A-03), with exposed pad not electrically connected.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with IDT5V9885BGI and ICS9FGP102AGT, the MPC9350AC uniquely combines on-chip crystal oscillator, static test mode, and PowerQUICC II–optimized output configuration-making it irreplaceable for legacy Freescale-based telecom designs requiring production validation and field serviceability.

Availability

MPC9350AC is available at Aetrix Electronics and suitable for telecom infrastructure, industrial networking, and embedded communications systems requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for MPC9350AC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors) was a leading designer of embedded processors and analog/mixed-signal ICs for automotive, industrial, and networking markets.

The MPC9350AC belongs to Freescale's Advanced Clock Drivers family, engineered specifically for high-reliability clock distribution in PowerQUICC-based communication systems demanding low skew, wide temperature operation, and robust PLL performance.

FAQ

What is the maximum output frequency supported by the MPC9350AC?

The MPC9350AC supports a maximum output frequency of 200 MHz when configured with ÷2 division from the 400 MHz VCO (FBSEL = 0). This occurs with fref = 12.5 MHz and FSELA = 0. Output frequencies scale down to 25 MHz with ÷8 division. All AC specifications-including skew and jitter-are guaranteed across the full 25–200 MHz range at both 2.5 V and 3.3 V supply conditions.

Does the MPC9350AC require external loop filter components?

No, the MPC9350AC does not require external loop filter components. Its fully integrated PLL design eliminates the need for external capacitors or resistors in the feedback path. This simplifies PCB layout, reduces bill-of-materials cost, and improves manufacturing yield. The internal PLL maintains stable lock across temperature and voltage variations without user-adjustable compensation networks.

How does the static test mode function on the MPC9350AC?

In static test mode (activated by pulling PLL_EN low), the MPC9350AC bypasses the PLL entirely and routes the TCLK input signal directly to the output dividers. This allows functional verification of clock distribution paths without waiting for PLL lock, supports boundary-scan testing, and enables clock injection during system debug. The minimum input frequency specification does not apply in this mode, permitting use with low-frequency test signals.

Can the MPC9350AC drive multiple transmission lines simultaneously?

Yes, the MPC9350AC can drive up to two 50 Ω series-terminated transmission lines per output due to its low 14–17 Ω output impedance. Each output delivers sufficient drive strength for incident-edge signaling on both lines, with measured skew delta <43 ps between loads. For parallel termination, only one 50 Ω line per output is supported to avoid excessive DC current draw. Fanout is effectively 1:18 in series-terminated configurations.

What is the purpose of separate VCCA and VCCO supply pins on the MPC9350AC?

The separate VCCA (PLL analog supply) and VCCO (I/O and core digital supply) pins isolate sensitive PLL circuitry from high-noise digital switching transients. VCCA powers only the VCO and phase detector, while VCCO powers output buffers and logic. This partitioning minimizes jitter induced by I/O activity. Recommended design practice includes RC filtering on VCCA-using a 8–15 Ω resistor and 0.01 µF + 22 µF capacitor-to attenuate 10 kHz–5 MHz noise that degrades PLL stability.