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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

NXP Semiconductors MPC940LAC

Name: MPC940LAC
Brand: NXP Semiconductors
SKU: MPC940LAC
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: MPC940LAC

Manufacturer:: NXP Semiconductors

Category:: Application Specific Clock/Timing

Package:: 32-LQFP

Datasheet:: MPC940LAC.pdf

Description:: IC CLOCK DIST CHIP 1:18 32-LQFP

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Product details

Overview

MPC940LAC from Freescale Semiconductor (formerly Motorola) is a 1:18 low-voltage clock distribution IC designed for high-speed synchronous systems. It supports dual-input selection (LVPECL or LVCMOS), delivers 18 LVCMOS outputs at 2.5V or 3.3V, achieves ≤150ps output-to-output skew, and operates up to 250MHz - making it suitable for Pentium II microprocessor clock tree distribution and series-terminated transmission line driving.

For engineers reviewing the MPC940LAC datasheet, MPC940LAC pinout, MPC940LAC application, or MPC940LAC equivalent, key selection considerations include input interface flexibility (LVPECL/LVCMOS), dual-supply configuration options (VCCI/VCCO), output drive strength for 50Ω termination, skew-critical timing integrity, and LQFP-32 package compatibility with high-density PCB layouts.

Technical Context

The MPC940LAC integrates a dual-mode input multiplexer selecting between differential LVPECL and single-ended LVCMOS reference clocks, with internal pull-up/pull-down resistors enabling unused inputs to float safely. Its output stage features low-impedance (18–28Ω) LVCMOS buffers optimized for driving two 50Ω series-terminated lines per output - delivering effective 1:36 fanout.

It supports three supply configurations: 3.3V core + 3.3V outputs, 3.3V core + 2.5V outputs, or 2.5V core + 2.5V outputs - with corresponding AC performance trade-offs (e.g., max frequency drops to 200MHz under 2.5V/2.5V operation). Output skew remains tightly controlled at ≤150ps (PECL/LVCMOS input) across all valid supply modes.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	18 LVCMOS clock outputs - enables single-chip distribution to multiple ASICs, FPGAs, or memory controllers.
Max output skew	150ps - ensures deterministic phase alignment across all 18 outputs for synchronous system timing closure.
Max input frequency	250MHz (at VCCI/VCCO = 3.3V) - supports high-speed CPU and bus clock domains including Pentium II front-side bus.
Output impedance	18–28Ω - matches 50Ω series-terminated transmission lines without external resistors, reducing BOM count and layout complexity.
Supply flexibility	Dual-rail: VCCI (core) and VCCO (I/O) independently set to 2.5V or 3.3V - allows mixed-voltage system integration and power optimization.
Input interface	LVPECL differential or LVCMOS single-ended - enables direct connection to MC100EP111 fanout buffers or standard logic-level clocks.
Package	32-lead LQFP (7×7mm, 0.8mm pitch, Case 873A–02) - balances thermal performance, routing density, and manufacturability in compact designs.

Pinout & Package

Package: 32-lead LQFP (7×7mm body, 0.8mm lead pitch, Case 873A–02), RoHS-compliant, surface-mountable with standard reflow profile.

Pin	Circuit Role	Design Meaning
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24	Q0–Q17, GNDO, GNDI, VCCI, VCCO	18 clock outputs (Q0–Q17), two ground planes (GNDO for outputs, GNDI for core), and separate core/output supply pins enable noise isolation and rail-specific decoupling.
25, 26, 27, 28, 29, 30, 31, 32	PECL_CLK, LVCMOS_CLK, LVCMOS_CLK_SEL, GNDO	Differential PECL clock input (25/26), LVCMOS clock input (27), clock source select (28), and auxiliary output ground (32) - supports dual-clock redundancy and test/system clock separation.

Key Features

Feature	Design Value
1:36 effective fanout	Each of 18 outputs drives two 50Ω series-terminated lines - eliminates need for external fanout buffers in mid-scale clock trees.
Configurable I/O voltage	VCCI and VCCO independently set to 2.5V or 3.3V - supports legacy 3.3V logic and modern 2.5V microprocessor I/O domains on same board.
Input-selectable clock source	LVCMOS_CLK_SEL pin selects between PECL_CLK (differential, high-frequency) and LVCMOS_CLK (single-ended, low-noise) - enables flexible clock architecture and test mode insertion.
Internal biasing	All digital inputs include factory-trimmed pull-up/pull-down resistors - simplifies PCB design by allowing unused control pins to remain unconnected.
Low-skew distribution	≤150ps output-to-output skew across full temperature/voltage range - meets tight setup/hold margin requirements for DDR SDRAM and high-speed ASIC interfaces.

Applications

Pentium II Microprocessor Clocking	High-Speed ASIC Timing Distribution
Use Scenario: Distributing synchronized clock signals to Pentium II CPU, northbridge, and memory controller on a desktop motherboard. IC Role / Device Role / Timing Role: Primary clock fanout buffer providing 2.5V LVCMOS clocks with sub-150ps skew to meet Intel's FSB timing specifications. Use Value: Eliminates discrete resistor networks and additional buffers while maintaining signal integrity across 18 critical clock loads.	Use Scenario: Driving clock inputs of multiple high-speed ASICs in telecom line cards requiring deterministic phase alignment. IC Role / Device Role / Timing Role: Low-skew clock distributor interfacing with LVPECL sources (e.g., MC100EP111) to feed parallel processing pipelines. Use Value: Enables simultaneous sampling across distributed logic blocks without added jitter or inter-chip skew penalties.
DDR SDRAM Interface Clocking	Test Equipment Clock Tree
Use Scenario: Generating matched clock pairs for DDR SDRAM data strobes and command/address latches in embedded systems. IC Role / Device Role / Timing Role: 2.5V LVCMOS clock generator with <150ps skew ensuring t_DS/t_DH margins are met across memory subsystem. Use Value: Reduces timing closure effort by guaranteeing output alignment within JEDEC-specified DDR setup/hold windows.	Use Scenario: Providing calibrated, multi-phase clocks to FPGA-based pattern generators and logic analyzers in ATE systems. IC Role / Device Role / Timing Role: Dual-input clock selector (LVCMOS test clock + LVPECL system clock) with programmable source switching via LVCMOS_CLK_SEL. Use Value: Supports in-system validation using production clock paths while enabling independent test clock injection without hardware modification.

Pentium II Microprocessor Clocking

High-Speed ASIC Timing Distribution

Use Scenario: Distributing synchronized clock signals to Pentium II CPU, northbridge, and memory controller on a desktop motherboard.

IC Role / Device Role / Timing Role: Primary clock fanout buffer providing 2.5V LVCMOS clocks with sub-150ps skew to meet Intel's FSB timing specifications.

Use Value: Eliminates discrete resistor networks and additional buffers while maintaining signal integrity across 18 critical clock loads.

Use Scenario: Driving clock inputs of multiple high-speed ASICs in telecom line cards requiring deterministic phase alignment.

IC Role / Device Role / Timing Role: Low-skew clock distributor interfacing with LVPECL sources (e.g., MC100EP111) to feed parallel processing pipelines.

Use Value: Enables simultaneous sampling across distributed logic blocks without added jitter or inter-chip skew penalties.

DDR SDRAM Interface Clocking

Test Equipment Clock Tree

Use Scenario: Generating matched clock pairs for DDR SDRAM data strobes and command/address latches in embedded systems.

IC Role / Device Role / Timing Role: 2.5V LVCMOS clock generator with <150ps skew ensuring t_DS/t_DH margins are met across memory subsystem.

Use Value: Reduces timing closure effort by guaranteeing output alignment within JEDEC-specified DDR setup/hold windows.

Use Scenario: Providing calibrated, multi-phase clocks to FPGA-based pattern generators and logic analyzers in ATE systems.

IC Role / Device Role / Timing Role: Dual-input clock selector (LVCMOS test clock + LVPECL system clock) with programmable source switching via LVCMOS_CLK_SEL.

Use Value: Supports in-system validation using production clock paths while enabling independent test clock injection without hardware modification.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock distribution applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MPC9109	Fewer outputs (1:9), lower max frequency (150MHz), no LVPECL input, single 3.3V supply only.	Suitable for cost-sensitive, lower-pin-count applications where 250MHz and dual-supply flexibility are unnecessary.	Select MPC9109 when system clock rates stay below 150MHz and only 3.3V I/O is required - reduces BOM cost and power consumption.
MPC942	Lower output impedance (~12Ω), higher drive capability, but no LVCMOS input option - LVPECL-only interface.	Better suited for ultra-low-impedance transmission line driving (e.g., backplane traces), but lacks input interface flexibility.	Choose MPC942 when driving unterminated or very long 50Ω lines where <15Ω Z_OUT is mandatory - accept loss of LVCMOS clock source option.

Compared with MPC940LAC, MPC9109 offers lower cost and power at reduced performance and feature set, while MPC942 provides superior drive strength for demanding interconnects but sacrifices input interface versatility - MPC940LAC uniquely balances skew, voltage flexibility, and dual-input support in a single LQFP package.

Availability

MPC940LAC is available at Aetrix Electronics and suitable for Pentium II microprocessor clocking, high-speed ASIC timing distribution, DDR SDRAM interface clocking, and test equipment clock tree applications requiring stable component supply and long-term obsolescence management.

Supply support for MPC940LAC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors) was a leading designer of high-performance analog and mixed-signal timing solutions, with deep expertise in clock distribution, PLLs, and interface ICs for computing and communications markets.

The MPC940LAC belongs to Freescale's Timing Solutions portfolio, engineered specifically for low-skew, multi-rail clock distribution in high-performance microprocessor and ASIC-based systems - emphasizing signal integrity, supply flexibility, and layout efficiency.

FAQ

What input clock standards does the MPC940LAC support?

The MPC940LAC supports two distinct input standards: differential LVPECL (via PECL_CLK pins 25/26) and single-ended LVCMOS (via LVCMOS_CLK pin 27). Selection is controlled by the LVCMOS_CLK_SEL pin (pin 28). This dual-input capability allows the MPC940LAC to interface directly with high-frequency LVPECL fanout buffers like the MC100EP111 or standard logic-level clocks, making MPC940LAC adaptable to diverse system clock architectures.

Can the MPC940LAC operate with mixed supply voltages?

Yes, the MPC940LAC supports independent core and I/O supply rails: VCCI (pins 19/20) powers the internal logic, while VCCO (pins 16/17) powers the output drivers. VCCI and VCCO can each be set to either 2.5V or 3.3V ±5%, enabling configurations such as 3.3V core with 2.5V outputs for Pentium II compatibility. This flexibility is explicitly defined in the DC characteristics tables and makes MPC940LAC suitable for mixed-voltage board designs.

What is the maximum output-to-output skew specification for the MPC940LAC?

The MPC940LAC guarantees a maximum output-to-output skew of 150ps across all 18 outputs under both LVPECL and LVCMOS input conditions, as verified in the AC Characteristics tables for all valid supply configurations (3.3V/3.3V, 3.3V/2.5V, and 2.5V/2.5V). This parameter is critical for synchronous system timing closure and is measured across the full operating temperature range (0°C to 70°C), confirming MPC940LAC's suitability for high-speed, skew-sensitive applications.

How many clock outputs does the MPC940LAC provide, and what are their electrical characteristics?

The MPC940LAC provides 18 LVCMOS-compatible clock outputs (Q0–Q17, pins 1–15, 21–24). Each output supports either 2.5V or 3.3V logic levels depending on VCCO, delivers ≥20mA drive strength, exhibits 18–28Ω output impedance, and maintains ≤150ps skew. These outputs are designed to drive 50Ω series-terminated lines directly - and each can drive two such lines, giving MPC940LAC an effective 1:36 fanout without external components.

Is the MPC940LAC pin-compatible with other devices in Freescale's clock distribution family?

No documented pin-compatible replacements exist for the MPC940LAC within Freescale's portfolio. While MPC9109 and MPC942 serve overlapping clock distribution functions, they differ in pin count (MPC9109 is 24-lead), pin assignment (e.g., no dedicated LVCMOS_CLK_SEL on MPC942), and supply pin mapping. The MPC940LAC's 32-lead LQFP footprint and specific pinout - including dual ground planes (GNDO/GNDI) and separated VCCI/VCCO - are unique to this device and not shared with alternatives, so PCB redesign is required when substituting.

MPC940LAC Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: -

Package/Case:: 32-LQFP

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: No

Main Purpose:: Intel CPU Servers

Input:: LVCMOS, LVPECL

Output:: LVCMOS

Number of Circuits:: 1

Ratio - Input:Output:: 2:18

Differential - Input:Output:: Yes/No

Frequency - Max:: 250MHz

Voltage - Supply:: 2.375V ~ 3.465V

Operating Temperature:: 0°C ~ 70°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 32-TQFP (7x7)

MPC940LAC FAQ

1.How can I place an order for MPC940LAC through Aetrix?

Please submit a Request for Quotation (RFQ) for MPC940LAC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MPC940LAC reliable?

The price and inventory of MPC940LAC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MPC940LAC is usually 5 days.

3.What payment methods are accepted for MPC940LAC?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MPC940LAC transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MPC940LAC?

MPC940LAC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MPC940LAC order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MPC940LAC?

For technical support, including MPC940LAC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MPC940LAC requirements.

6.How does Aetrix verify that MPC940LAC is sourced from the original manufacturer or authorized distributors?

All MPC940LAC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MPC940LAC meets industry standards.

7.What is the process for return or replacement of MPC940LAC?

All MPC940LAC units undergo pre-shipment inspection (PSI). If there is an issue with MPC940LAC, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MPC940LAC part is unused and in its original packaging.

Return procedure for MPC940LAC:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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