NXP Semiconductors MPC9772FAR2

Overview

MPC9772FAR2 from Freescale Semiconductor (formerly Motorola) is a 3.3V, 1:12 PLL-based LVCMOS clock generator designed for low-skew, high-performance clock distribution in networking, computing, and telecom systems. It delivers up to 240 MHz output frequency, <250 ps output-to-output skew across 12 LVCMOS outputs, and supports three independent output frequency banks with programmable dividers and 180° phase shift capability for bank C.

For engineers reviewing the MPC9772FAR2 datasheet, MPC9772FAR2 pinout, MPC9772FAR2 application, or MPC9772FAR2 equivalent, this device is selected for zero-delay clock fanout, multi-frequency synchronous timing, and power-aware clock stop control in mid-to-high-end embedded timing subsystems.

Technical Context

The MPC9772FAR2 implements a fully integrated PLL architecture with separate VCO and output divider banks (A/B/C), enabling independent frequency synthesis per bank using FSEL_A/B/C[1:0] controls. Its feedback path uses QFB→FB_IN with selectable dividers (M = ÷4 to ÷40), and VCO_SEL extends usable reference range via internal ÷1/÷2 post-division.

It features dual LVCMOS reference inputs (CCLK0/CCLK1), crystal oscillator interface (XTAL_IN/XTAL_OUT), synchronous clock stop via serial STOP_DATA/STOP_CLK interface, and QSYNC synchronization pulse generation aligned to coincident rising edges of QA and QC banks - all operating within –40°C to +85°C ambient temperature.

Key Specifications

Pinout & Package

Package: 52-lead LQFP (Case 848D), 10 mm × 10 mm × 1.4 mm body, 0.5 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PLL clock generator applications.

Compared with ICS85310AGI-01LFT and Si5338A-A-GM, the MPC9772FAR2 uniquely balances 12 LVCMOS outputs, integrated crystal support, zero-delay capability, and industrial temperature range - making it optimal for cost-constrained, high-fanout, single-ended timing in telecom infrastructure.

Availability

MPC9772FAR2 is available at Aetrix Electronics and suitable for network switch timing, multi-core CPU clock trees, baseband radio synchronization, and optical transport line card designs requiring stable component supply across extended product lifecycles.

Supply support for MPC9772FAR2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors) is a leader in high-performance timing solutions, specializing in PLL-based clock generators for communications and computing infrastructure.

The MPC9772FAR2 belongs to Freescale's TIMING SOLUTIONS product line, engineered specifically for low-skew, multi-frequency clock distribution in carrier-grade networking and enterprise computing platforms.

FAQ

What is the maximum output frequency supported by the MPC9772FAR2?

The MPC9772FAR2 supports a maximum output frequency of 240 MHz under PLL-locked conditions, as confirmed in Table 10 of the datasheet. This applies to ÷2 output configurations (e.g., VCO=480 MHz, VCO_SEL=÷2, NA=÷2). At full industrial temperature (–40°C to +85°C), the guaranteed maximum is 230 MHz. The device achieves this while maintaining <250 ps output-to-output skew and <30 ps RMS phase jitter (at VCO=400 MHz, ÷8 feedback).

Does the MPC9772FAR2 require an external crystal or can it use an external clock source?

The MPC9772FAR2 supports both options: it includes an on-chip crystal oscillator circuit for direct connection to a 10–25 MHz fundamental-mode crystal (XTAL_IN/XTAL_OUT), and also accepts two LVCMOS-compatible external clock inputs (CCLK0 and CCLK1). The REF_SEL pin selects between crystal and LVCMOS reference, and CCLK_SEL chooses between CCLK0 and CCLK1 - enabling clock redundancy and flexible system-level timing architecture.

How does the clock stop function work on the MPC9772FAR2?

The MPC9772FAR2 implements individual clock stop via a 3-wire serial interface (STOP_CLK, STOP_DATA, and implicit START bit). A 12-bit register controls enable/disable of QA0–3, QB0–3, and QC1–3 (QC0 and QFB are non-stoppable). Writing '0' stops the output in logic low state - eliminating runt pulses - while '1' enables normal operation. The interface operates up to 20 MHz, allowing real-time power management in response to processor load or thermal events.

What is the purpose of the QSYNC output on the MPC9772FAR2?

The QSYNC output on the MPC9772FAR2 generates a synchronization pulse aligned to coincident rising edges of Bank A (QA) and Bank C (QC) outputs. Its pulse width equals the period of the higher-frequency bank, and it asserts one full period before the aligned edge. This signal serves as a system-level timing reference for frame alignment, data capture strobes, or multi-device synchronization - especially valuable when QA and QC frequencies have non-integer ratios (e.g., 3:2, 4:3).

Can the MPC9772FAR2 be used in zero-delay clock buffer applications?

Yes, the MPC9772FAR2 supports zero-delay operation by routing QFB to FB_IN externally, closing the PLL feedback loop. In this configuration, the PLL aligns the rising edge of QFB with the reference input edge, effectively canceling propagation delay. The resulting insertion delay is dominated by static phase offset (±166 ps at 50 MHz), output skew (<250 ps), and I/O jitter (≤30 ps RMS), enabling sub-500 ps deterministic latency - verified in Figure 8 and Applications section of the datasheet.