Monolithic Power Systems Inc. MPQ28261DL-LF-P

Overview

MPQ28261DL-LF-P from Monolithic Power Systems is a synchronous step-down DC/DC converter IC with integrated 120mΩ high-side and 20mΩ low-side MOSFETs, delivering up to 3A continuous output current across a 4.5V–21V input range. It operates at a fixed 500kHz switching frequency, features 1% reference voltage accuracy (603mV), external soft-start control via SS pin, and open-drain power-good (PG) output - deployed in DSL modems, set-top boxes, and telecom infrastructure for stable point-of-load regulation.

For engineers reviewing the MPQ28261DL-LF-P datasheet, MPQ28261DL-LF-P pinout, MPQ28261DL-LF-P application, or MPQ28261DL-LF-P equivalent, key selection criteria include input voltage range compatibility, thermal shutdown threshold (150°C), PG delay timing (~¼ SS time), and QFN14 (3×4mm) layout constraints for high-current SW and GND paths.

Technical Context

The MPQ28261DL-LF-P uses peak-current-mode control with a fixed 500kHz oscillator and internal 0.6V reference, enabling fast transient response and stable loop behavior without external compensation. Its error amplifier drives COMP voltage to regulate inductor current, while hiccup-mode over-current protection activates when VFB drops below 70% of reference and current limit is exceeded.

It integrates a 5.1V VCC regulator powered from VIN, bootstrap circuitry for high-side gate drive (BST pin), and independent AGND/SYSTEM GND separation requiring PCB-level connection. Thermal shutdown triggers at 150°C with 25°C hysteresis, and UVLO activates at 4.0V rising threshold on VIN-derived VCC rail.

Key Specifications

Pinout & Package

MPQ28261DL-LF-P is housed in a thermally enhanced 3mm × 4mm, 14-pin QFN package with exposed thermal pad (pins 12–13). The package supports high-power density layouts with low θ_JA = 48°C/W on 4-layer PCBs and requires solder paste stencil optimization for the exposed pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down converter applications.

Compared with MP2315DJ-LF-Z and RT7272BGJ8F, the MPQ28261DL-LF-P uniquely balances 3A capability, 120mΩ/20mΩ MOSFETs, PG+SS functionality, and 21V input limit - making it optimal for telecom and broadband equipment where reliability, sequencing, and thermal performance are critical.

Availability

MPQ28261DL-LF-P is available at Aetrix Electronics and suitable for DSL modems, set-top boxes, and telecom remote terminals requiring stable component supply, RoHS-compliant packaging, and long-term production continuity.

Supply support for MPQ28261DL-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MPQ28261 belongs to MPS's high-efficiency synchronous buck converter product line, engineered for compact, thermally constrained applications in broadband communications and consumer electronics where integration, accuracy, and reliability are prioritized.

FAQ

What is the minimum recommended input capacitance for MPQ28261DL-LF-P?

A minimum 22µF X5R/X7R ceramic capacitor is required at the IN pin, placed directly adjacent with wide traces and multiple vias. An additional 0.1µF ceramic capacitor must be added in parallel for high-frequency decoupling. Total RMS current rating must exceed 1.5A to handle worst-case ripple at VIN = 2×VOUT.

Can MPQ28261DL-LF-P operate with a pre-biased output?

Yes - the device supports pre-biased start-up. When VOUT is pre-charged, the IC disables both HS and LS switches until the SS capacitor voltage exceeds the sensed FB voltage. This prevents reverse current flow and ensures controlled ramp-up without output collapse or inductor saturation.

How is the soft-start time calculated for a given SS capacitor value?

Soft-start time is calculated as t_SS (ms) = (0.6V × C_SS [nF]) / 12µA. For example, a 47nF capacitor yields t_SS ≈ 2.35ms. This linear relationship is guaranteed by internal 12µA current source and 0.6V reference threshold, validated across -40°C to +125°C.

What is the maximum allowable output capacitance?

The maximum tested output capacitance is 1100µF, verified under 3A load with Chroma 63030 electronic load in CCH mode. Larger values may affect stability or soft-start behavior and require loop compensation verification per application conditions.

Does MPQ28261DL-LF-P require an external bootstrap diode?

An external bootstrap diode (e.g., 1N4148) from VCC to BST is optional and recommended only when duty cycle exceeds 65% - typically at VOUT ≥ 3.3V with VIN ≤ 5V. It improves high-side gate drive strength and efficiency under heavy load at high duty cycles.

What is the thermal resistance (θ_JA) for the QFN14 package?

θ_JA is 48°C/W when mounted on a standard 4-layer JEDEC PCB per JESD51-7. This value assumes full connection of the exposed thermal pad to an internal ground plane with ≥6 thermal vias (0.3mm diameter). Layout deviations increase junction temperature significantly.

How does the power-good (PG) signal behave during thermal shutdown?

During thermal shutdown, the PG pin is actively pulled low by an internal NMOS transistor regardless of FB voltage. PG remains low until the device fully restarts post-cooldown and VFB stabilizes above 90% of 603mV for ≥¼ SS time - ensuring PG only asserts after full regulation recovery.