Monolithic Power Systems Inc. MPQ3428AGL-AEC1-Z

Overview

MPQ3428AGL-AEC1-Z from Monolithic Power Systems is an AEC-Q100 Grade 1 qualified synchronous boost converter delivering up to 19A switch current, operating at 600kHz fixed frequency, with 3V–20V input range and integrated 18mΩ low-side MOSFET. It provides input disconnect via CLDR-driven external MOSFET, programmable input average current limit (54mV sense threshold), and thermal shutdown at 150°C - deployed in automotive eCall and telematics power rails where input isolation and transient robustness are critical.

For engineers reviewing the MPQ3428AGL-AEC1-Z datasheet, MPQ3428AGL-AEC1-Z pinout, MPQ3428AGL-AEC1-Z application, or MPQ3428AGL-AEC1-Z equivalent, key selection criteria include its AEC-Q100 qualification, 19A internal switch limit, QFN-22 (3mm×4mm) package thermal resistance (θJA = 48°C/W), input disconnect control logic, and COMP/SS pin configurability for loop stability and soft-start tuning.

Technical Context

The MPQ3428AGL-AEC1-Z implements a peak current-mode, constant-frequency boost architecture with dual current-sensing paths: internal sensing (CLDR = GND) enabling 19A cycle-by-cycle peak current limiting, or external sensing (CLDR floating) supporting programmable average input current regulation via VCL = 54mV and RSENSE. Its error amplifier features 300V/V gain and 160μA/V transconductance, with COMP pin directly controlling duty cycle through buffered reference comparison.

It integrates a bootstrap-regulated 5V SDR driver for synchronous rectification, BST-powered gate drive with UVLO protection, and EN-controlled micro-power startup (VEN-ON = 1.33V) with programmable VIN UVLO hysteresis. Protection includes linear-charge OCP hiccup (0.5ms blanking), output SCP, thermal shutdown (150°C trip, 25°C hysteresis), and <1μA shutdown current.

Key Specifications

Pinout & Package

MPQ3428AGL-AEC1-Z is housed in a thermally enhanced QFN-22 package (3mm × 4mm, 0.5mm pitch), with exposed thermal pad for PCB heat sinking. Pin 1 is marked by dot; top view orientation follows standard QFN layout with SW, PGND, and AGND pins distributed for low-inductance power routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous boost converter applications.

Compared with LM5122MQ/NOPB and TPS61088RHLR, MPQ3428AGL-AEC1-Z uniquely combines AEC-Q100 Grade 1 qualification, integrated 19A/18mΩ switch, input disconnect capability, and programmable average current limit - making it the only option qualified for safety-relevant automotive boost applications requiring VIN-to-VOUT isolation and thermal resilience.

Availability

MPQ3428AGL-AEC1-Z is available at Aetrix Electronics and suitable for automotive telematics, eCall emergency systems, smart latch actuators, and infotainment power supplies requiring stable component supply, AEC-Q100 compliance, and long-term production continuity.

Supply support for MPQ3428AGL-AEC1-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with core expertise in DC-DC conversion, motor drivers, and LED lighting controllers.

The MPQ3428A product line delivers automotive-grade synchronous boost converters optimized for eCall, telematics, and infotainment subsystems - emphasizing input disconnect safety, wide VIN operation, and AEC-Q100 reliability under harsh thermal and electrical conditions.

FAQ

What is the purpose of the CLDR pin, and how does it enable input disconnect?

The CLDR pin drives the gate of an external high-side MOSFET to physically isolate the input supply from the output during shutdown or output short-circuit events. When CLDR is pulled low (e.g., by internal logic during fault), the MOSFET turns off, breaking the VIN–VOUT path. This prevents backfeed, protects upstream battery systems, and meets ISO 16750-2 load-dump survivability requirements in automotive applications.

Can MPQ3428AGL-AEC1-Z operate with input voltage below 3V?

No - the absolute minimum operating input voltage is 3V per datasheet specifications. Below this, the internal regulator cannot sustain VDD bias, and the 18mΩ power switch fails to turn on reliably. The device enters undervoltage lockout (UVLO) with 2.68V typical turn-on threshold and 250mV hysteresis, ensuring clean startup only within the validated 3V–20V range.

How is the 54mV current-sense threshold used to set input current limit?

The 54mV (typ) V_CL threshold is compared against the voltage across an external R_SENSE placed between IN and SENSE. Using I_IN(AVG) = V_CL/R_SENSE, a 4.5mΩ resistor sets a 12A average input limit. This configuration requires CLDR floating and is validated for hiccup-free operation under sustained overload, unlike peak-current limiting which triggers immediate shutdown.

Why does the MPQ3428AGL-AEC1-Z use separate AGND and PGND pins?

AGND provides a quiet reference for sensitive analog circuits (FB, COMP, SENSE), while PGND carries high di/dt switch currents. Separating them prevents ground bounce from corrupting feedback accuracy or causing instability. Layout best practice requires connecting AGND to the quiet side of the input capacitor and tying both grounds to the thermal pad only at a single point near the IC.

What happens during thermal shutdown, and how does recovery work?

When junction temperature reaches 150°C, internal thermal protection disables switching and pulls CLDR low to engage input disconnect. The device remains latched off until temperature falls to 125°C (25°C hysteresis), then automatically resumes operation. This cycle prevents cumulative thermal stress and is validated across -40°C to +125°C ambient per AEC-Q100 Grade 1 requirements.

Is the BST pin required for normal operation, and what capacitor value is recommended?

Yes - BST supplies the 5V gate drive for the SDR synchronous rectifier driver. A 0.1μF X7R ceramic capacitor between BST and SW is mandatory; insufficient capacitance causes SDR dropout under low-duty-cycle conditions (e.g., high VOUT/VIN ratio), degrading efficiency and increasing heat in the external rectifier MOSFET.