Monolithic Power Systems Inc. MPQ5073GG-AEC1-Z

Overview

MPQ5073GG-AEC1-Z from Monolithic Power Systems is an AEC-Q100 qualified 2A load switch with programmable current limit, 50mΩ R_DS(ON), 0.5V–5.5V input range, soft-start control via external capacitor, and push-pull PG indicator - deployed in automotive infotainment power rails and ADAS domain controllers for controlled hot-swap sequencing.

For engineers reviewing the MPQ5073GG-AEC1-Z datasheet, MPQ5073GG-AEC1-Z pinout, MPQ5073GG-AEC1-Z application, or MPQ5073GG-AEC1-Z equivalent, key selection criteria include programmable ILIM resistor configuration, <200ns short-circuit response, thermal shutdown hysteresis (30°C), output discharge function, and QFN-12 (2mm×2mm) package thermal performance under 125°C junction operation.

Technical Context

The MPQ5073GG-AEC1-Z integrates a charge-pump–driven DMOS FET with sense-FET–based current limiting, enabling precise 1.4A–2.2A programmable OCP via ILIM-to-ground resistor (e.g., 13kΩ → ~2.2A). Its soft-start slew rate is set by an external SS capacitor charged by a 11µA internal current source, scaling V_OUT rise at 5× the SS voltage ramp rate.

Power-good detection uses a differential comparator monitoring V_IN–V_OUT gap (140–450mV threshold), asserting PG high after 50µs delay when regulation is stable; short-circuit protection triggers a 200ns fast-off circuit at ~7A peak, followed by 80µs auto-retry with reduced current limit until thermal shutdown at 150°C.

Key Specifications

Pinout & Package

MPQ5073GG-AEC1-Z uses a thermally enhanced QFN-12 (2mm × 2mm) package with exposed thermal pad (pins 6, 11, and exposed pad connected to VIN); footprint optimized for ≤80°C/W θ_JA on 4-layer PCBs per JESD51-7.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar load switch applications.

Compared with TPS22919DBVR and NIS5020MN, MPQ5073GG-AEC1-Z uniquely combines AEC-Q100 qualification, programmable OCP, integrated PG, and output discharge in a 2mm×2mm footprint-enabling compact, self-contained power sequencing in safety-critical ADAS nodes without external support components.

Availability

MPQ5073GG-AEC1-Z is available at Aetrix Electronics and suitable for automotive infotainment systems, ADAS camera modules, and telematics control units requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MPQ5073GG-AEC1-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-efficiency analog and mixed-signal ICs for power management, motion control, and interface applications.

The MPQ5073 belongs to MPS's automotive-grade load switch product line, engineered specifically for robust hot-swap control, fault containment, and power-rail sequencing in AEC-Q100–compliant vehicle subsystems.

FAQ

What is the minimum recommended soft-start capacitor value for MPQ5073GG-AEC1-Z?

The datasheet specifies a minimum 4.7nF ceramic capacitor on the SS pin to ensure stable soft-start behavior. Using smaller values risks uncontrolled V_OUT rise times dominated by MOSFET gate charge, potentially triggering current limit during startup. Larger values (e.g., 100nF) extend ramp time to >5ms for 2A loads, reducing inrush stress on input capacitors.

How does the ILIM resistor affect current-limit accuracy across temperature?

The MPQ5073GG-AEC1-Z uses a fixed sense-FET ratio (S ≈ 33,000) and internal reference; ILIM resistor tolerance and tempco directly impact OCP accuracy. With a 1% 25ppm/°C resistor, current limit drift remains within ±3% from −40°C to +125°C, verified in electrical characteristics tables for V_CC = 3.3V and 5.0V conditions.

Can the PG pin drive a 10kΩ pull-up to 3.3V without external buffering?

Yes-the PG pin is a push-pull output rated for 3.2V high and 0.3V low at 1mA sink/source. Driving a 10kΩ pull-up to 3.3V draws only 330µA, well within its 1mA specification. No external buffer is needed for interfacing with standard CMOS inputs like FPGA configuration pins or microcontroller GPIOs.

Is the exposed thermal pad electrically connected to any internal node?

Yes-the exposed pad (pins 6, 11, and thermal pad) is internally tied to VIN. It must be soldered to a dedicated VIN copper pour with ≥4 thermal vias to ground plane to achieve the specified 80°C/W θ_JA and sustain 1.6W continuous power dissipation per absolute maximum ratings.

What happens during simultaneous short-circuit and thermal overload events?

Short-circuit protection takes precedence: the 200ns fast-off circuit disables the FET before thermal accumulation dominates. If the fault persists, repeated 80µs retries cause cumulative heating; once junction temperature reaches 150°C, thermal shutdown overrides retry logic and holds the device disabled until temperature falls below 120°C (150°C − 30°C hysteresis).

Does the output discharge function activate during normal enable/disable transitions?

Yes-the 200Ω internal discharge FET engages immediately upon EN deassertion, regardless of load current magnitude. It remains active until V_OUT drops below ~0.4V, ensuring rapid rail collapse even under light loads (e.g., <100µA), critical for preventing unintended wake-up in low-power sleep states.

How does UVLO interact with VCC supply sequencing in multi-rail systems?

VCC UVLO threshold is 2.6–2.95V with 200mV hysteresis. If VCC ramps before VIN, the device remains disabled until both VCC exceeds UVLO and EN is asserted. This prevents partial-enable states during asymmetric power-up, ensuring reliable initialization in systems with independent 3.3V bias and 5V main rails.