Monolithic Power Systems Inc. MPQ6533GUE-AEC1-Z

Overview

MPQ6533GUE-AEC1-Z from Monolithic Power Systems is a three-channel automotive gate driver IC designed to control six external N-channel MOSFETs in brushed DC motor applications. It integrates an LDO (12 V ±1 V), bootstrap charge pump for 100% duty cycle high-side drive, reverse-battery protection charge pump (VRG ≈ VIN +12 V), current-sense amplifier (gain configurable 20–250 V/V), and SPI-configurable protection features including adjustable dead time (50 ns–6.4 µs) and short-circuit thresholds (110–810 mV). Used in automotive actuators requiring AEC-Q100 Grade 1 qualification.

For engineers reviewing the MPQ6533GUE-AEC1-Z datasheet, MPQ6533GUE-AEC1-Z pinout, MPQ6533GUE-AEC1-Z application, or MPQ6533GUE-AEC1-Z equivalent, key selection considerations include its integrated current sensing without shunt resistors, configurable OCP thresholds per channel, reverse-battery protection via VRG output, QFN-32 (5 mm × 5 mm) thermal pad package, and SPI-based diagnostics for fault reporting and parameter tuning in safety-critical motor control systems.

Technical Context

The MPQ6533 implements independent three-channel half-bridge pre-driver architecture with dedicated high-side (GHA/GHB/GHC) and low-side (GLA/GLB/GLC) gate outputs per channel, each supporting 0.8 A source / 1 A sink drive strength. Bootstrap capacitor charging is synchronized to low-side conduction, enabling continuous high-side operation up to 40 V input.

Its diagnostic subsystem includes SPI-accessible registers for real-time monitoring of over-current (per-channel V_DS threshold), open/short load detection (via OLSx-controlled biasing), thermal warning (125°C) and shutdown (165°C), UVLO on VIN (4.45 V typ) and VG (5.4 V typ), and fault latching behavior controlled by OCMD bit.

Key Specifications

Pinout & Package

MPQ6533GUE-AEC1-Z is housed in a thermally enhanced QFN-32 (5 mm × 5 mm) package with exposed thermal pad, optimized for automotive motor control PCB layouts requiring low thermal resistance (θ_JA = 36°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar three-channel automotive gate driver applications.

Compared with DRV3205-Q1 and BD6212F-E2, MPQ6533GUE-AEC1-Z uniquely combines SPI-configurable protection, reverse-battery VRG output, and shuntless current sensing in a single AEC-Q100 Grade 1 package-making it optimal for high-integrity brushed DC motor systems requiring field-upgradable fault thresholds and diagnostic traceability.

Availability

MPQ6533GUE-AEC1-Z is available at Aetrix Electronics and suitable for automotive actuator design, brushed DC motor driver development, and AEC-Q100-compliant embedded control systems requiring stable component supply across extended production lifecycles.

Supply support for MPQ6533GUE-AEC1-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with core expertise in DC-DC converters, motor drivers, and automotive-grade analog solutions.

The MPQ6533 belongs to MPS's automotive pre-driver product line, engineered specifically for AEC-Q100-compliant brushed DC motor control in harsh environments-emphasizing integrated diagnostics, reverse-battery resilience, and minimal external component count.

FAQ

What is the purpose of the VRG pin and how is it used?

The VRG pin outputs ≈VIN +12 V generated by an internal charge pump to drive the gate of an external N-channel MOSFET for reverse-battery protection. It is disabled during startup and sleep mode. To use it, connect a 100 kΩ resistor between the external MOSFET's gate and source, and a 0.22 µF ceramic capacitor between CP1 and CP2. The ENVRG bit in the FAULT register must be set to 1 after startup to enable VRG.

How does the MPQ6533 perform current sensing without a shunt resistor?

The MPQ6533 measures the voltage drop (V_DS) across the low-side MOSFET when it is fully on, amplifies it with an integrated current-sense amplifier (gain configurable from 20 to 250 V/V), and outputs the result on the CSO pin. This eliminates the power loss and board space required for external shunt resistors while maintaining accuracy within ±10 mV offset.

What happens during the bootstrap refresh sequence?

When any BSTx voltage falls below 2.95 V, the MPQ6533 initiates a bootstrap refresh: it sequentially turns on each low-side MOSFET to recharge its corresponding bootstrap capacitor via the internal LDO (VG). This sequence takes 1–2 ms and occurs automatically-no host intervention required-and resumes normal operation once all BSTx voltages exceed threshold.

Can the MPQ6533 drive high-side P-channel MOSFETs?

No-the MPQ6533 is designed exclusively for N-channel high-side MOSFETs driven via bootstrap or charge pump (VRG). Its GHA/GHB/GHC outputs are sourced from internal charge pumps referenced to SHA/SHB/SHC, making them incompatible with P-MOSFET gate drive requirements (which need negative V_GS or source-referenced drive). External level-shifting circuitry would be required and is not supported by the device architecture.

How is open/short load detection implemented?

Open/short load detection uses a 1 V, 200 µA current source enabled per channel via the OLSx bit. When activated, the corresponding OUTx bit reflects the voltage at SHx: OUTx = 1 indicates no short (voltage ~1 V); OUTx = 0 indicates short-to-ground or short-to-VIN. Detection is performed with all channels disabled and requires SPI readback of the OUT register-no external components needed.

What is the minimum recommended bootstrap capacitor value?

MPS specifies ceramic capacitors between BSTx and SHx pins but does not define a minimum capacitance in the datasheet. However, typical designs use 100 nF X7R ceramics. The critical constraint is ESR: low-ESR ceramic types are mandatory to ensure sufficient charge transfer during high-frequency PWM switching and prevent bootstrap voltage droop that could trigger UVLO and refresh cycles.

Is the nFAULT pin latched or auto-clearing?

The nFAULT pin is active-low and remains asserted until the root cause fault condition is cleared *and* the corresponding fault flag (e.g., OCLx, OTS, BSUVx) is manually cleared by writing 1 to that bit via SPI. If OCMD = 0, the affected channel auto-recovers after ~1 ms; if OCMD = 1, the channel stays latched off until both the fault bit and OCMD are reset-enabling fail-safe system response.