Monolithic Power Systems Inc. MPQ6541GQKTE-AEC1-P

Overview

MPQ6541GQKTE-AEC1 from Monolithic Power Systems is a three-phase BLDC motor power stage IC integrating six N-channel MOSFETs, three half-bridge drivers, six pre-drivers, two gate driver supplies, and three bidirectional current-sense amplifiers. It delivers 8A continuous or 12A peak output current, operates from 4.75V to 40V input, and features AEC-Q100 Grade 1 qualification for automotive motor control applications such as electric power steering and HVAC blowers.

For engineers reviewing the MPQ6541GQKTE-AEC1 datasheet, MPQ6541GQKTE-AEC1 pinout, MPQ6541GQKTE-AEC1 application, or MPQ6541GQKTE-AEC1 equivalent, key selection criteria include its integrated current sensing with ±25µA offset, 15mΩ HS/LS R_DS(on), internal charge pump enabling 100% duty cycle, thermal shutdown at 150°C, and TQFN-26 wettable flank package for automated optical inspection.

Technical Context

The MPQ6541GQKTE-AEC1 implements independent PWM/ENBL logic control per phase (MPQ6541-AEC1 variant), with synchronous rectification triggered by inductive flyback voltage thresholds. Its charge pump generates V_CP = VIN + 5V at 2MHz switching frequency to drive high-side FETs, while an internal LDO regulates VG to ~5.5V for low-side gate drive.

Safety architecture includes cascaded protection: UVLO (4.4V threshold with 470mV hysteresis), OVP (48V rising threshold), cycle-by-cycle over-current detection on both HS and LS paths (10–19A HS, 17.5–25A LS trip), and thermal shutdown with 25°C hysteresis-each asserting open-drain nFAULT.

Key Specifications

Pinout & Package

The MPQ6541GQKTE-AEC1 is housed in a thermally enhanced TQFN-26 (6mm × 6mm) package with wettable flanks for solder joint inspection. The exposed thermal pad (Pin 18 GND) must be soldered to a large PCB copper area with ≥9 thermal vias for effective heat dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar three-phase BLDC motor driver applications.

Compared with MPQ6541AGQKTE-AEC1, the MPQ6541GQKTE-AEC1 offers simpler MCU interface but less flexible timing control; versus DRV8305-Q1, it trades voltage headroom and raw efficiency for integration density and reduced system-level component count.

Availability

MPQ6541GQKTE-AEC1 is available at Aetrix Electronics and suitable for electric power steering, HVAC blower motors, and engine cooling fans requiring stable component supply across automotive production lifecycles.

Supply support for MPQ6541GQKTE-AEC1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over 20 years of automotive-grade product development experience.

The MPQ6541-AEC1 belongs to MPS's AEC-Q100-qualified motor driver product line, engineered specifically for space-constrained, thermally demanding automotive BLDC and PMSM applications where integration, reliability, and functional safety are critical.

FAQ

What is the maximum allowable PCB temperature rise for continuous 8A operation?

With the TQFN-26 package mounted on a 4-layer PCB per JESD51-7, θ_JA = 21.4°C/W. At 8A and 15mΩ R_DS(on), total conduction loss is 1.92W per phase (5.76W total). This yields a 123°C rise above ambient, requiring ambient ≤27°C for 125°C junction limit. Thermal vias and copper area reduce this significantly in practice.

How does the automatic synchronous rectification improve efficiency?

By actively turning on the LS-FET during inductive flyback instead of relying on the body diode, conduction losses drop from ~1.2V × I_LOAD (diode drop) to ~0.015Ω × I_LOAD² (R_DS(on)). At 8A, this reduces dissipation from 9.6W to 0.96W per phase-cutting total recirculation loss by 90% and enabling quieter, cooler operation.

Can the current-sense outputs drive an ADC directly?

No. SOx pins are current-output (not voltage-output) with ±25µA offset and require external termination. Connect a precision resistor (e.g., 5kΩ) between SOx and VREF (typically 5V) to generate a ratiometric voltage: V_OUT = VREF + (I_LOAD × R_TERM) / 11600. This ensures ADC codes scale linearly with motor current.

What happens during an over-voltage event above 48V?

When VIN exceeds 48V (OVP threshold), all six MOSFETs are immediately disabled to protect downstream motor windings and gate drivers. Unlike UVLO or OCP, nFAULT is not asserted-allowing the system to distinguish OVP from other faults. Operation resumes automatically once VIN falls below 46.7V (48V – 1.3V hysteresis).

Is the nSLEEP pin compatible with automotive wake-up protocols?

Yes. nSLEEP has an internal 500kΩ pull-down, ensuring safe default disable state during power-up. Wake-up latency is 1ms after nSLEEP rises, compatible with CAN/LIN-based wake patterns. The 1µA sleep current meets UNECE R100 Class 3 requirements for always-on vehicle modules.

Why are there two LSS pins and two VIN pins?

LSS pins (10,12) and VIN pins (23,25) are duplicated to minimize PCB trace resistance and inductance in high-current paths. Each LSS carries return current for one or more phases; splitting them reduces ground bounce and improves current-sense accuracy. Dual VIN pins distribute input current, lowering IR drop and thermal stress on the package.

Does the charge pump require special capacitor dielectric types?

Yes. CP1–CP2 requires a 100nF X7R ceramic capacitor rated for ≥VIN, and VCP–VIN requires a 1µF X7R ceramic capacitor rated for ≥10V. X7R ensures stable capacitance across temperature and DC bias-critical for maintaining gate drive voltage under load. NP0/C0G is acceptable but less cost-effective; Y5V/Z5U must be avoided due to severe capacitance loss at bias.