Monolithic Power Systems Inc. MPQ6628GF-AEC1-P

Overview

MPQ6628GF-AEC1-P from Monolithic Power Systems is an AEC-Q100 Grade 1 qualified octal half-bridge motor driver IC with integrated DMOS power MOSFETs, operating from 5.5V to 40V input and delivering up to 0.8A per channel. It features serial SPI control (up to 5MHz), comprehensive diagnostics (open-load, over-current, thermal warning/shutdown, UV/OV detection), and dual VS supply rails for flexible motor winding routing. It is deployed in automotive body control modules for driving solenoids, valves, and small DC motors.

For engineers reviewing the MPQ6628GF-AEC1-P datasheet, MPQ6628GF-AEC1-P pinout, MPQ6628GF-AEC1-P application, or MPQ6628GF-AEC1-P equivalent, key selection criteria include its 1.3Ω typical HS+LS R_DS(ON), -40°C to +150°C junction temperature range, TSSOP-28EP package with exposed thermal pad, and AEC-Q100 qualification for automotive reliability.

Technical Context

The MPQ6628GF-AEC1-P integrates eight independent half-bridge output stages, each with high-side and low-side DMOS FETs, controlled via a 16-bit SPI interface supporting channel-selectable configuration (HB[6:1] or HB[8:7]). Its dual VS supply architecture (VS1 for outputs 1/2/5/7/8 and VS2 for outputs 3/4/6) enables isolated power domains for mixed-voltage motor loads.

Diagnostic functionality is implemented at silicon level: open-load detection triggers on LS current <16mA for >350μs; over-current protection activates at 1.3A typical with 25μs shutdown delay; thermal pre-warning asserts at 120–140°C and shutdown at 150–175°C, both with 20°C hysteresis. All fault states are latched and reported via DO serial output.

Key Specifications

Pinout & Package

MPQ6628GF-AEC1-P is housed in a thermally enhanced TSSOP-28EP package (4.4mm × 9.7mm, 0.65mm pitch) with an exposed copper pad on the bottom for PCB-level heat dissipation. The package supports JEDEC MSL Level 2A moisture sensitivity and is RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal half-bridge driver applications.

Compared with TBD72004AFG and DRV8876PWPR, MPQ6628GF-AEC1-P delivers higher channel density, lower system-level BOM cost, and richer diagnostic telemetry in a single AEC-Q100-qualified package - making it optimal for space-constrained automotive body electronics where functional safety and serviceability are prioritized.

Availability

MPQ6628GF-AEC1-P is available at Aetrix Electronics and suitable for automotive body control modules, industrial valve actuation systems, and off-road equipment motor control requiring stable component supply, AEC-Q100 compliance, and long-term lifecycle support.

Supply support for MPQ6628GF-AEC1-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MPQ6628 belongs to MPS's automotive-grade motor driver product line, engineered specifically for AEC-Q100-compliant body electronics applications requiring high integration, robust diagnostics, and minimal external components.

FAQ

What is the maximum allowable VS supply voltage for continuous operation?

The MPQ6628GF-AEC1-P supports continuous operation up to 40V on VS pins, with an absolute maximum rating of 45V. Operation beyond 40V risks triggering the OVLO threshold (33–39V), causing automatic shutdown. For 24V systems experiencing load dump, external clamping is recommended to stay within the 40V operational limit.

How does the open-load detection behave when OLSD_EN is disabled?

When OLSD_EN is cleared (0), the MPQ6628 still detects open-load conditions (LS current <16mA for >350μs) and sets the OLD status bit, but does not disable the affected output stage. This allows the system to log faults without interrupting operation - useful for non-critical loads where graceful degradation is preferred over immediate shutdown.

Can VS1 and VS2 be powered from different voltage sources?

Yes - VS1 and VS2 are electrically isolated internal supplies. VS1 powers outputs 1/2/5/7/8 and the charge pump; VS2 powers outputs 3/4/6. They may be supplied from separate rails (e.g., 12V for VS1, 24V for VS2) as long as each remains within 5.5–40V and shares a common ground. External connection between VS1 and VS2 is only required if using a single supply.

What happens to the output state during EN pin assertion?

Pulling EN low forces all eight half-bridges into high-impedance (Hi-Z) state, disables the charge pump, resets internal SPI registers, and reduces total supply current to 1–5μA. Outputs remain safely off until EN is pulled high again, at which point the device resumes operation with default register values (all HBEN = 0, HBCNF = 0).

Is the DO pin truly tri-state when CS is high?

Yes - when CS is high, the DO pin enters a high-impedance (tri-state) condition, allowing multiple MPQ6628 devices to share a common DO bus in daisy-chain configurations. The DO output only becomes active (driven) on the falling edge of CS and remains valid until the next rising edge of CS, synchronized to CLK.

Does the thermal pre-warning (TW) bit auto-clear after temperature drops?

Yes - the TW bit automatically clears when the junction temperature falls below the thermal warning recovery threshold (TJW minus 20°C hysteresis). Unlike latched faults (OC, TSD, OLD), TW is a dynamic flag indicating real-time thermal stress, enabling adaptive derating strategies without requiring an SRR or reset.

What SPI frame format is required for writing to channels 7 and 8?

To configure outputs 7 and 8, the 16-bit SPI frame must set bit[14] = 1 (CH_SEL = 1). Bits[13:8] then control HBEN7/HBEN8 and HBCNF7/HBCNF8, while bits[7:0] are reserved except for OVLO enable. Frames with CH_SEL = 0 only affect channels 1–6 and ignore bits intended for 7/8.